Module engine 

The engine as Verilog: the sequencer running the machine’s jobs (crate::spatial::decode_engine::machine) over the token-row store and the card’s memory, the units doing each job’s work.

The host writes the engine’s tables (tables) through its port, an entry a cycle: the jobs’ words (table 0), the step’s row table (1: each row’s region, its position and its ring index), the store’s slots (2: each slot’s first beat and beats a row), the tensors (3) and the rotary tables (4), each block’s place in a region (5), and the store (6), which it reads back a beat at a time. A step runs from the word job_at to the word job_end, a job after another; the host has put each row’s embedding in the store, so the engine starts after the embedding’s job. The card’s memory is a port of whole 64-byte lines, read a line a request and written a line at a time under a byte mask. A job starts at a word, runs to its end and stops; the engine is busy from a step’s start until its last job is done and every write the step made is on the card.

A vector job’s passes each load the vector unit’s registers a beat at a time — a token-row’s beat from the store, a tensor’s or a rotary table’s line from memory, a ring row’s line as the state stores it (binary16 halves widened) — run the job’s instructions one after another on super::simd, then store a beat at a time: into the store under a lane mask, or into memory as the sink keeps it (f32, binary16 halves, int8 codes, a binary16 scale) under a byte mask. The vector unit’s registers and scalars carry over between passes; a pass reads only what it loads and what its own instructions write, so what a pass leaves never reaches the next. A slot’s lanes past the width of the vector a job last wrote there are no vector’s: nothing reads them, so a job neither clears nor keeps them.

Structs

AttendJob

The word a hybrid engine’s core gives its attention side with a token-row of an attention job (Streaming::attention), its fields from the lowest bit, each 32 bits but the last: the row’s region (its first line), its block’s keys’, values’, key scales’ and value scales’ offsets in it, the cached heads, the row’s positions (its own and every one before), the score scale’s bits, the store beats of the row’s query and of its output, and the query heads (16 bits).

EngineParams

What an engine is printed for: the most token-rows a step holds, the most beats a vector register holds and the most a Hadamard or rotary operand does, the store’s beats, the words of the step’s jobs, the tables’ entries, every block format its matrices are in with the most blocks a row of that format holds, and the function units its vector unit’s sixteen lanes share.

GdnJob

The word a hybrid engine’s core gives its recurrence unit with a job of a lazily flushed memory’s token-rows (Streaming::recurrence), its fields from the lowest bit: the job’s rows (16 bits); its block’s memory’s and log’s offsets in a row’s region and a log entry’s bytes, its key and value heads, a log entry’s values’, decay exponents’ and gates’ first elements, the read-out’s scale’s bits (32 bits each); the store slots of the rows’ query, output, key heads, value heads, decay exponents and gates (5 bits each) and the values’ first element in theirs (20 bits); the tokens a flush takes (8 bits), and whether the state stores binary16. The fast side lays each row’s region and store beats from its copies of the rows and slots tables (logos_gdn_rows).

HardFloat

The floating-point DSP block’s add, and its multiply unless the multiplies stay soft, as the oracle measured them (crate::codegen_sva::fp_hard::Block): a hybrid engine whose fast side builds logos_fadd_p, and logos_fmul_p given a product, on the block (crate::codegen_sva::fp_hard::hard_verilog_for), each the soft unit’s ports and latency, the logic around the block correcting what it computes otherwise. The add computes the engine’s own arithmetic; the multiply the arithmetic of fp_unit: at FpUnit::Soft the engine’s, so a block whose multiply decides a product tiny before the engine does is refused, at FpUnit::Hard the card’s (FpUnit::CARD), the arithmetic the numerics of an fp_unit: Hard knob point multiply by.

HybridJob

The word a hybrid engine’s core gives its streaming unit with a matvec job, its fields from the lowest bit: the stream entry’s first line’s seven words (super::streaming::StreamEntry: the seventh its greedy flag and, from bit 1, its fold), its four tile runs (its other two lines), the input slot’s and the output slot’s table entries, the step’s token-rows and whether it runs two words.

Streaming

The streaming unit of a hybrid engine (super::streaming::streaming_verilog), in the fast clock beside the engine’s: the column set it is built for and the image layout its matrices lie in on the channels, whose stripe is the row pairs a channel’s share of a stripe holds; and whether the recurrence unit and the vector unit’s side stand beside it.

Tables

The engine’s tables for one step, as the host writes them.

VectorSideJob

The word a hybrid engine’s core gives its vector unit’s side with a vector job (Streaming::vectors), its fields from the lowest bit: the place of the job’s header in the job words, the step’s token-rows (16 bits), and whether the state stores binary16.

Constants

CONV_PATH_VREGS

The vector registers of the vector unit of a side whose convolutions run on their path (Streaming::with_conv_path), half of the sixteen a job’s fields can name: every job the machine lowers but a convolution names fewer.

ENGINE_MIN_DIVIDE

Fast clock cycles an engine clock cycle must span at least: the crossing takes the shell’s values two cycles after the engine clock’s rising edge, the core reads its memories the cycle after the falling edge, and the crossing holds what the engine gives the shell from the cycle after that, all before the next rising edge.

FUNCTION_UNITS

The function units the vector unit’s sixteen lanes share: a quarter of a unit a lane, the vector unit’s largest part (each unit an exp, a reciprocal, an ln and a reciprocal square root) in a quarter of the area.

PORT_PIPES

The pipes each channel’s fast port crosses at the engine’s edge, each way: a path from a channel’s bank at the die’s edge to the fast side a pipe each part of the way.

VECTOR_PASSES_MAX

The most passes a vector unit’s side runs at once (Streaming::with_vector_passes): each pass holds its own scalar registers and running sums, so the latency every instruction pays is shared by the group.

Functions

behind

The part of a streaming unit’s name a recurrence carrying its memories as flush adds: +behind<T> for a trailing flush of T, nothing otherwise.

bridge_verilog

logos_engine_bridge, the crossing between the engine clock the shell runs in (sclk) and the user clock it is divided from (fclk), its every register in the user clock: each value the shell gives the engine taken straight into a register (cap_) two user cycles after the engine clock’s rising edge, so the core, stepping at the next rising edge and reading its memories the cycle after the middle, sees the values the shell set at the edge before, as an engine clocked by the shell’s clock does; each value the engine gives the shell taken straight into a register (held_) two user cycles after the middle, holding past the next rising edge, when the shell takes it.

census

The instance statements under top in verilog, counted through the hierarchy: every module top instantiates, directly or through the modules it instantiates, with the number of statements that reach it. A statement inside a generate loop counts once.

compose

Verilog sources as one: every module once — a module two sources define being the same text in each — with the text before it, the macros it reads among it.

engine_verilog

The engine for p, with the vector unit, the array’s columns for every format p names, the activation quantizer they and the query heads share and the f32 units they are built from; a hybrid engine’s matvec jobs on its streaming unit instead of the columns, the quantizer the query heads’ alone.

hard_float_model

The floating-point DSP block a simulation of an engine on hard stands in for the device’s (fourteennm_fp_mac, crate::codegen_sva::fp_oracle::hard_model_verilog): the measured semantics of its multiply and add at their measured depths, the multiply-add as deep as the deeper of them. With the multiplies soft no instance takes the block’s multiply, and the stand-in’s is the add’s.

hard_float_verilog

The engine verilog (engine_verilog’s text) with its f32 adds, and its multiplies given a product block, on the floating-point DSP block hard: logos_fadd_p (and logos_fmul_p) replaced by the block’s wrappers, the same ports and latencies. Every instance of either is the fast side’s; refuses an engine whose core reaches one, the core stepping at its enables where the wrappers run free.

logged

The tokens a Gated-DeltaNet memory carried as flush logs before the engine replays them: 1 for a memory rewritten every pass. A unit that replays a whole log at once runs these; a trailing flush runs on head lanes alone (recurrence_log).

recurrence_log

The tokens a recurrence unit’s log holds at its longest and the window a trailing flush replays a window behind: logged’s, or a trailing flush’s two windows and its window.

simulation_twin

The engine verilog (engine_verilog’s text) as a simulator runs it: the core’s clock gated to the user cycles the core steps in (fedge) or reads its memories in (cr), the one difference. Every register of the core steps under step_en and every memory reads under read_en and writes under ce, so a rising edge of the user clock with neither high changes nothing in the core, and without those edges a simulator evaluates the core’s logic in two user cycles of an engine cycle instead of in every one. The gate is taken at the falling edge, so the gated clock rises only with the user clock. Refuses an engine whose core holds state any other way, or enables an instance by anything but its own step_en and read_en. A simulation model only: a PR persona gates no clock, every global network being the FIM’s.

tables

The tables of jobs over layout, the store laid out as store, for the step’s rows.

tables_at

tables with every address the engine reads the card’s memory at — a tensor’s, a rotary table’s, a sequence’s region — placed by place: the hybrid engine’s tables over its compacted memory (crate::spatial::decode_engine::physical::Compaction::place). A tensor place gives no place, one the hybrid engine streams and never reads by address, has address 0.