Module rtl 

The decode engine’s units as Verilog, each computing exactly what its super::numerics function computes.

Modules

act_quant

The activation quantizer (crate::spatial::decode_engine::numerics::quantize) as Verilog: a block of 32 f32 values to its 4-bit-significand scale and its codes.

array

The array’s processing element as Verilog: two weight rows’ partial dot products with one token-row’s activations, four multiply-adds a DSP block.

attend

The attention unit’s vector path as Verilog: one query head over its sequence’s cached rows, exactly as crate::spatial::decode_engine::numerics::attend_vector computes it.

column

The streaming engine’s matrix columns as Verilog: a matrix streamed block-major within groups of row pairs, each (row, token-row) still the row’s blocks added in order, so every result is crate::spatial::decode_engine::numerics::dot’s.

engine

The engine as Verilog: the sequencer running the machine’s jobs (crate::spatial::decode_engine::machine) over the token-row store and the card’s memory, the units doing each job’s work.

fp32

f32 multiply and add as the engine computes them (crate::spatial::decode_engine::numerics::fmul, fadd): IEEE binary32 rounded to nearest with ties to even, a denormal operand read as a zero of its sign, a result below the normals rounded at the denormals’ precision and then flushed to a zero of its sign (so only a result that rounds up to the least normal survives), every NaN the one quiet NaN 0x7fc00000. Beside them, the binary16 codec between those f32s and the f16 a stored state, a cache scale or the vector unit’s f16 rounding keeps.

gdn

The Gated-DeltaNet row engine as Verilog: one value row of a memory through one token (crate::spatial::decode_engine::numerics::gdn_row), sixteen elements a cycle.

lane

The block-scale lane as Verilog (crate::spatial::decode_engine::lane::lane): a weight block’s excess partial sums to its signed sums, the two scaled terms, their exact sum rounded once to f32, and the f32 add into the row.

matvec

The array’s matrix-vector step as Verilog: one weight block of two rows against one token-row’s activations, from the GGUF bytes to each row’s next f32 (crate::spatial::decode_engine::numerics::dot under ActScaling::PerBlock, a block at a time).

ram

The engine’s memories as the FPGA’s block RAM holds them.

simd

The vector unit as Verilog: sixteen f32 lanes running the instruction set of crate::spatial::decode_engine::vector over vector and scalar registers, one sixteen-element row a cycle.

stream

The image stream engine: one memory channel’s tiles of the weight image in, the tiles’ rows out as 64-byte beats.

streaming

The streaming engine’s units composed from the columns, the feeds and the activation quantizer.

vector

The vector units’ functions as Verilog, each the same f32 operations in the same order as its numerics function (crate::spatial::decode_engine::numerics): exp, recip, rsqrt, ln, ln1p, softplus, sigmoid and silu, over the engine’s f32 multiply and add, with the integer steps the functions take between them — the nearest integer of an f32, an integer as an f32, a power-of-two scaling — and their tables as ROMs.

vector_side

A hybrid engine’s vector jobs in the user clock (super::engine::Streaming::vectors): logos_vector_side runs a crate::spatial::decode_engine::machine::Job::Vector job as the core’s vector-job states do — the job’s descriptors from the job words, then each pass of a row and a head: the loads into the vector unit’s registers, the micro-program on the user clock’s vector unit (logos_simd_p, super::simd::simd_p_verilog), the stores — on its own copies of the core’s tables, written as the core’s are, the token-row store’s user-clock port and the fast port onto the channels (super::super::physical::fast_port_verilog).

weights

The weight decoders as Verilog: each GGUF block format the array reads, unpacked in place into one form the array and the block-scale unit share.