Module simd 

The vector unit as Verilog: sixteen f32 lanes running the instruction set of crate::spatial::decode_engine::vector over vector and scalar registers, one sixteen-element row a cycle.

A vector register holds up to ROWS rows of sixteen lanes and its length. An instruction over a vector walks its rows: elementwise instructions write lane by lane, Dot and Sum accumulate each lane over the rows and fold the lanes by the pairwise tree once the rows are done, Max and AbsMax keep each lane’s largest and fold the lanes the same way, a largest zero +0, and ArgMax keeps each lane’s largest with the first index holding it and folds the lanes to the larger, the lower index of equals. Hadamard runs its stages in place: the strides below sixteen within each row, the strides of sixteen and up between rows, a pair of rows read at once and written in two cycles. Rotate copies its operand, then turns sixteen pairs from one read of the rows they sit in, and writes those rows one a cycle under lane masks. Scalar instructions take a cycle. Lanes past a register’s length stay out of every reduction and every write. The functions run on FU function units, a divisor of sixteen, each in LANE_FUNC_STAGES stages a cycle apart: a Map’s rows go in a slice of FU lanes a cycle, 16 / FU cycles a row and one row after another, each row written when its last slice’s values are out, and a ScalarMap takes the first unit’s stages.

The registers live in block RAM (rtl::ram), a bank a register with three copies written alike: copy A read at the row at hand, or at the engine’s row while the unit is idle, copies B and C at a Hadamard partner row and a rotary block’s two rows, and one write a bank a cycle.

logos_simd_p is the same unit for the user clock (simd_p_verilog): every register and value the same, on the pipelined f32 units and function units (logos_lane_func_p, LANE_FUNC_P_LATENCY), its registers block RAM read on the rising edge. An instruction’s rows stream through its units a row a clock and are written as they come out; Dot and Sum add a row each add’s latency, each lane’s running sum through one pipelined add, and fold the lanes by the pipelined tree; the maxima take a row a clock and fold in four registered levels; a Hadamard stage streams its rows, one stage after another; a rotary block is read, turned and written before the next.

An instruction is 64 bits: [3:0] the opcode, [7:4] the operation or function (Rotate’s NEOX flag), [11:8] a, [15:12] b (Rotate’s cosines), [19:16] d, [23:20] the scalar operand (Rotate’s sines, a multiply-add’s vector addend), [63:32] a constant (encode). A multiply-add’s product goes into its sum as the multiply’s result goes into an add after it.

Constants

LANE_FUNC_P_LATENCY

Clocks a pipelined function unit’s value (logos_lane_func_p) takes from its operand: the operand decoded and registered; the exponential; the add after it; the reciprocal, the logarithm, the reciprocal square root and one less than the sum, each held to the slowest; ln1p’s error, its product and its sum; the choice registered.

LANE_FUNC_STAGES

Cycles a function unit’s value takes from its operand (logos_lane_func with STAGED): the exponential; the add after it; the reciprocal, the logarithm, the reciprocal square root and one less than the sum; ln1p’s correction and the choice. No stage is deeper than one of the functions’ cores, so the vector unit’s longest path is a core’s, not the chain of them.

SIMD_P_READ_LATENCY

Clocks the user clock’s vector unit (logos_simd_p) takes from a row asked (rd_row, rd_reg) to its word on rd_data: the row registered, then read.

Functions

decode

The instruction an instruction word stands for, or None for a word no instruction encodes to.

encode

The instruction word for op.

simd_p_verilog

The vector unit in the user clock (logos_simd_p), with its pipelined function units (logos_lane_func_p), the pipelined f32 units, the functions and the block RAM it is built from, beside the vector unit it is held to (simd_verilog).

simd_verilog

The vector unit, with the f32 units, the functions, the tree and the block RAM it is built from.