Function simulation_twin 

pub fn simulation_twin(verilog: &str) -> String

The engine verilog (engine_verilog’s text) as a simulator runs it: the core’s clock gated to the user cycles the core steps in (fedge) or reads its memories in (cr), the one difference. Every register of the core steps under step_en and every memory reads under read_en and writes under ce, so a rising edge of the user clock with neither high changes nothing in the core, and without those edges a simulator evaluates the core’s logic in two user cycles of an engine cycle instead of in every one. The gate is taken at the falling edge, so the gated clock rises only with the user clock. Refuses an engine whose core holds state any other way, or enables an instance by anything but its own step_en and read_en. A simulation model only: a PR persona gates no clock, every global network being the FIM’s.