Function bridge_verilog 

pub fn bridge_verilog() -> String

logos_engine_bridge, the crossing between the engine clock the shell runs in (sclk) and the user clock it is divided from (fclk), its every register in the user clock: each value the shell gives the engine taken straight into a register (cap_) two user cycles after the engine clock’s rising edge, so the core, stepping at the next rising edge and reading its memories the cycle after the middle, sees the values the shell set at the edge before, as an engine clocked by the shell’s clock does; each value the engine gives the shell taken straight into a register (held_) two user cycles after the middle, holding past the next rising edge, when the shell takes it.