pub fn hard_float_verilog(verilog: &str, hard: &HardFloat) -> StringExpand description
The engine verilog (engine_verilog’s text) with its f32 adds, and its multiplies given a product block, on the
floating-point DSP block hard: logos_fadd_p (and logos_fmul_p) replaced by the block’s wrappers, the same ports
and latencies. Every instance of either is the fast side’s; refuses an engine whose core reaches one, the core
stepping at its enables where the wrappers run free.