Expand description
The array’s matrix-vector step as Verilog: one weight block of two rows against one token-row’s activations, from
the GGUF bytes to each row’s next f32 (crate::spatial::decode_engine::numerics::dot under
ActScaling::PerBlock, a block at a time).
The two rows’ blocks pass their decoders; their codes meet the token-row’s activation words in the processing
elements a 4-bit digit at a time — one digit for a code of four bits or fewer, two for a wider one, the high digit’s
partials weighted by 16 — each 16-element unit’s partials summed from its two elements; the units’ Σ q·a′, the
words’ Σ a′, the decoders’ Σ q and multipliers feed each row’s lane, which adds the block into the row.
An activation code is 16 bits: a one-word code in −127..127 crosses as a + 128; a two-word code as its signed
high byte plus 128 and its unsigned low byte. logos_matvec_block #(UNITS, DIGITS) is the format-free step;
logos_matvec_<format> puts the format’s decoders in front of it; logos_matvec_engine_<format> is one column of
the array: the weight stream’s two rows a beat, every token-row’s codes held, a token-row a cycle, every
token-row’s two rows emitted once their last block is in.
Functions§
- matvec_
verilog - The matrix-vector step for every format, with the lane, the processing element, the decoders, the f32 units and the block RAM they are built from.