Module fp32 

f32 multiply and add as the engine computes them (crate::spatial::decode_engine::numerics::fmul, fadd): IEEE binary32 rounded to nearest with ties to even, a denormal operand read as a zero of its sign, a result below the normals rounded at the denormals’ precision and then flushed to a zero of its sign (so only a result that rounds up to the least normal survives), every NaN the one quiet NaN 0x7fc00000. Beside them, the binary16 codec between those f32s and the f16 a stored state, a cache scale or the vector unit’s f16 rounding keeps.

The modules are combinational; a pipelined copy for timing keeps their function and the lock holds both.

Constants

F32_TO_F16_LATENCY

Clocks from an f32 entering logos_f32_to_f16_p to its binary16 leaving: its candidates, round bits and class registered, then the rounding and the choice.

FADD_LATENCY

Clocks from a pair of operands to their sum in logos_fadd_p.

FMUL_LATENCY

Clocks from a pair of operands to their product in logos_fmul_p.

TREE16_LATENCY

Clocks from sixteen lanes to their tree’s sum in logos_tree16_p.

Functions

fp32_verilog

logos_fmul(a, b) -> y and logos_fadd(a, b) -> y, and their pipelined copies logos_fmul_p (three registered stages) and logos_fadd_p (four), a pair of operands a clock, each the same function of the operands its latency before; logos_tree16, the pairwise tree of sixteen lanes’ sums (crate::spatial::decode_engine::numerics::fdot’s fold), and its pipelined copy logos_tree16_p on logos_fadd_p, sixteen lanes a clock; and the binary16 codec logos_f32_to_f16 and logos_f16_to_f32 (crate::spatial::decode_engine::numerics::f32_to_f16, crate::model::quant::f16_to_f32): nearest even, binary16 denormals kept, an f32 denormal a zero of its sign, past the top infinite; and the rounding’s pipelined copy logos_f32_to_f16_p (F32_TO_F16_LATENCY).