Module lane 

The block-scale lane as Verilog (crate::spatial::decode_engine::lane::lane): a weight block’s excess partial sums to its signed sums, the two scaled terms, their exact sum rounded once to f32, and the f32 add into the row.

logos_lane #(UNITS) takes, per 16-element unit, the high word’s Σ q·a′ and Σ a′ (the only word of a one-word code), the low byte’s alike, the weight image’s Σ q, and the unit’s multipliers c and n; per block the format’s offset z, the two binary16 scales, the activation scale m·2^e, whether the code has two words, and the row’s running f32. logos_round88 is the one rounding: an exact signed integer times a power of two to f32, nearest even, a result below the normals flushed to a zero of its sign, past the top infinite.

logos_lane_value_p #(UNITS, WORDS) is the lane up to its rounding, pipelined for the streaming engine: a block’s inputs a clock, and LANE_VALUE_LATENCY clocks later the block’s f32 value, the f32 the lane adds into its row (the lane from −0, which every value leaves as it is), its stages each unit’s signed sums and their products, the units’ sums in fours, their sum, the two scaled terms, their exact sum, and the rounding in ROUND88_P_LATENCY stages of its own (logos_round88_p: the magnitude; each byte’s leading one; the leading one; the significand kept with its round and sticky bits; the rounding and the f32). Its multipliers are the bytes every decoder’s c and n are, its offset term a shift (every format’s offset is zero or a power of two). Built for one activation word (WORDS 1), a unit’s signed sum Σ (q − z)·a over its 16 elements is within 19 bits (every format’s offset code within ±128, every one-word activation code within ±127: at most 16·128·127 = 260,096), so a pair of units’ products is one DSP block’s two 18×19 multipliers summed; built for two, each unit’s product is one wide multiplier.

logos_lane_slim_p #(UNITS, WORDS) is logos_lane_value_p for a block of one scale — every unit’s multiplier 1 and its offset multiplier 0, Q8_0’s and Q4_0’s blocks — at the same latency: the units’ signed sums summed, the one scaled term and the rounding, no unit multiplies and one product a block.

Constants

LANE_VALUE_LATENCY

Clocks from a block’s inputs to its value in logos_lane_value_p: four to the exact sum, then the rounding.

ROUND88_P_LATENCY

Clocks from logos_round88_p’s operands to their f32.

Functions

lane_verilog

Every module of the lane, with the f32 adder it accumulates through.