Function emit_wpe_user_project_verilog 

pub fn emit_wpe_user_project_verilog(
    name: &str,
    caps: [usize; 10],
    backend: MemBackend,
    memory: &OffchipMemory,
    caravel: &WpeCaravel,
) -> Result<String, WpeCaravelUnplaceable>

The full-interface Caravel user macro wpe_user_project: the engine wpe_soc_<name> with memory’s memories off-chip, clocked by WPE_CLOCK, its UART and PSRAM on caravel.pins (a bidirectional SIO pad is driven exactly while the edge drives it: io_oeb is its active-low enable), every other GPIO an input.

The engine’s reset crosses into its clock domain through two flops, asserted at once and released on the second edge after its source falls. The source is wb_rst_i, or logic-analyzer probe 0 while the management SoC drives it (la_oenb[0] low, efabless’s override in user_proj_example.v): at power-on the PLL is bypassed and user_clock2 is the pad clock, caravel_clocking.v moves it to the PLL with a plain select between the two, and the firmware resets the engine after that switch, which a chip reset cannot do without bypassing the PLL again. The Wishbone slave runs on wb_clk_i, acknowledges every access and reads zero, so the management SoC never waits on the user area; the rest of the logic analyzer and the interrupts are unused.