Module wpe_caravel 

The whole-program engine as a Caravel user project: the off-chip engine (wpe_offchip) on the Caravel user interface, its UART and its PSRAM on user GPIOs, clocked by user_clock2 (WPE_CLOCK) and reset by the management SoC.

One pin plan (WpePins) is the source of every place a pin appears: the macro’s io_out/io_oeb wiring, the power-on GPIO modes of user_defines.v, and the testbench that runs a program through the Caravel pins against the part’s pin model. The UART’s bit period is derived from the clock and the baud rate and checked against both the UART’s tolerance and the off-chip memories’ loading stalls.

Structs

BringupVector

One program of the bring-up bench: the bytes the host sends and the result the model computes for them.

HarnessDelay

Caravel’s harness between a user-area port and its pad, as efabless characterizes it for user projects: the IO_SYNC budget of the scaffold’s base_user_project_wrapper.sdc, generated from Caravel’s own STA by get_cup_sdc.py. io_out reaches its pad in 3.90..=9.12 ns, io_oeb in 2.34..=9.32 ns, and a pad reaches io_in in 1.26..=4.55 ns.

WpeCaravel

The engine on Caravel: its clock period, the host’s baud rate, and the pin plan.

WpePins

Where the engine’s pins land on Caravel’s user GPIOs.

Enums

GpioMode

How a GPIO comes up at power-on, as user_defines.v names the mode.

WpeCaravelUnplaceable

Why the engine cannot be wired to Caravel as asked.

Constants

BOARD_FLIGHT_MAX_PS

The carrier board’s trace between a pad and the part, each way: at most 1 ns, about 15 cm of FR-4. A requirement the board must meet, not a property of the die.

BRINGUP_PRELOAD

A weighted sum over a streamed preload of 40 weights: 41 heap words, more than a heap cache of eight two-word lines holds, so the weights come back from the part.

BRINGUP_TEXT

Text built, compared and shown over the wire.

CARAVEL_FIRST_USER_IO

CARAVEL_IO

Caravel’s user GPIOs: io_in/io_out/io_oeb[37:0], of which 0..=4 carry the housekeeping SPI and JTAG.

CARAVEL_IO_MAX

CARAVEL_IO_MIN

UART_MAX_ERROR_PPM

A UART tolerates a little over 2% of accumulated error across a frame, split between both ends.

WPE_CARAVEL

The shipped wiring: the pin plan, the 21 ns clock (47.62 MHz on user_clock2) and a 115200-baud host.

WPE_CARAVEL_BACKEND

The config image reaches the walk through a registered port only under the config-in-BRAM backend.

WPE_CARAVEL_CAPS

The shipped cap profile, [NREG, MAXBLK, MAXCELL, MAXWR, MAXARG, MAXLIV, MAXK, HEAP, DEPTH, MAXV].

WPE_CARAVEL_NAME

The engine the Caravel user project carries: wpe_soc_caravel.

WPE_CLOCK

The harness clock the engine runs on. Caravel’s chip signoff times the core clock, wb_clk_i, at 25 ns, and the management SoC and the bus run on it; user_clock2 is the PLL’s 90-degree phase through a divider of its own, so the engine runs at its own period while the management SoC stays at the one the chip is signed for.

WPE_PINS

The shipped plan: the UART on GPIO 8 and 9, the PSRAM’s CE#, SCLK and SIO[3:0] on 10..=15 — clear of the housekeeping pins and of the management UART on 5 and 6.

Functions

emit_wpe_user_defines

user_defines.v: every user GPIO’s power-on mode, from the pin plan.

emit_wpe_user_project_testbench

The off-chip engine’s host testbench, driving wpe_user_project through its Caravel pins at the engine’s clock: the UART on the plan’s GPIOs, the part’s pin model on the PSRAM GPIOs (a pad driven exactly while its io_oeb is low), every PSRAM pin reaching the part pads after the macro drives it and the part’s data reaching io_in pads.in_ps after the part drives it, the management SoC’s clock and reset, and an idle Wishbone. A pin driven the wrong way at any point after reset fails the run with PIN-DIRECTION.

emit_wpe_user_project_verilog

The full-interface Caravel user macro wpe_user_project: the engine wpe_soc_<name> with memory’s memories off-chip, clocked by WPE_CLOCK, its UART and PSRAM on caravel.pins (a bidirectional SIO pad is driven exactly while the edge drives it: io_oeb is its active-low enable), every other GPIO an input.

emit_wpe_user_project_wrapper_testbench

emit_wpe_user_project_testbench driving the cell that is fabricated: Caravel’s user_project_wrapper, the engine reached through its mprj.

wpe_caravel_bringup_vectors

The bring-up bench’s programs, in the order it sends them: the text program, then the preload summed over all 40 weights and over the first 17.

wpe_caravel_memory

The shipped off-chip memories: the edge’s cycle counts are timed at 16 ns with two engine cycles per SCLK half (a 64 ns SCLK), so every slower clock meets tPU, tRST, tCPH, tCLK and tACLK too, and its bursts are cut for 40 ns, where tCEM leaves two words a line; heap, frame stack and config image each get eight such lines.

wpe_caravel_overlay_files

The emitted files of the WPE submission’s overlay, by path under it: the GPIOs’ power-on modes, and the bring-up directory — the bench driving the fabricated user_project_wrapper at the chip’s clock with every PSRAM pin at the harness’s slowest delay and the board’s longest flight, and the program bytes, per-program lengths and model results it reads.

wpe_caravel_wire

The bytes a host sends the Caravel chip to run cfg on params with heap_init streamed ahead of the run, or every table of the shipped profile the program overflows as (engine parameter, demand, cap). The chip traps a call deeper than its frame stack and a heap access past its region on its own; every other table is checked here, before anything is sent, because an overflowing table would be loaded into the wrong words.

wpe_psram_read_sta_tcl

The OpenSTA script that closes a PSRAM read through the hardened macro, at the corner lib characterizes and over the parasitics in spef: the SCLK edge’s latest arrival at its pad-side port, the SIO data constrained to arrive the read’s round trip outside the macro after it (WpeCaravel::read_round_trip_ps), and the worst slack of that data into its capture flops at the edge the half SCLK period puts it on. The first two terms are the macro’s own share of the read window, which the harness check alone cannot see. Prints SCLK_ARRIVAL_NS <ns> and SIO_CAPTURE_SLACK_NS <ns>.