Struct OffchipMemory 

pub struct OffchipMemory {
    pub edge: PsramEdge,
    pub heap: Option<PsramCache>,
    pub frames: Option<PsramCache>,
    pub cells: Option<PsramCache>,
}

The engine memories behind one PSRAM edge, each with its own cache; None keeps a memory on the die.

Fields

edge: PsramEdge

heap: Option<PsramCache>

frames: Option<PsramCache>

cells: Option<PsramCache>

The config image, as three lanes of one word per cell — {code, kind}, {op1, op0}, {op3, op2} — each behind a cache of this geometry.

Implementations

impl OffchipMemory

pub fn roles(&self) -> Vec<ArrayRole>

The floorplan roles this engine takes off the die.

pub fn part_words(&self) -> u64

The part’s words within the edge’s word address.

pub fn regions(&self, caps: [usize; 10]) -> Vec<Region>

Each off-chip memory’s region for the cap profile caps, largest first so every region is aligned to its own size: the three cell lanes (MAXCELL words each), the frame stack (DEPTH x NREG) and the heap (HEAP), each rounded up to a power of two. An index past its memory’s cap wraps inside its own region and never reaches another memory’s.

pub fn check( &self, caps: [usize; 10], backend: MemBackend, ) -> Result<(), OffchipUnplaceable>

Refuse a combination the engine cannot build: nothing off-chip, the config image off-chip without the registered config port, or regions the part cannot hold.

pub fn loading_stall_cycles(&self) -> u64

The longest stall the loader can meet while bytes are still arriving. Until it takes the go byte the loader touches the part only to write — one config-image field per four bytes, one preloaded heap word per eight — and the walk fetches no cells, so the worst is one write miss in the heap or cell caches that evicts a dirty line. Stalls in the run are not bounded by the UART: the host sends nothing until the result frame is back.

pub fn check_uart(&self, clks_per_bit: u64) -> Result<(), OffchipUnplaceable>

Refuse a UART that could lose a byte. The receiver holds one byte while the FSM is stalled, so a byte is lost only if another completes before the stall ends; requiring every loading stall to be shorter than a byte means no byte ever waits at all. The first access to the part comes no sooner than wire_bytes_before_first_part_access bytes after reset, and the edge must have initialized the part by then, or that access would wait out the power-up too.

pub fn min_clks_per_bit(&self) -> u64

The fastest UART (fewest system cycles per bit) check_uart accepts.

Trait Implementations

impl Clone for OffchipMemory

fn clone(&self) -> OffchipMemory

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for OffchipMemory

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl PartialEq for OffchipMemory

fn eq(&self, other: &OffchipMemory) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for OffchipMemory

impl Eq for OffchipMemory

impl StructuralPartialEq for OffchipMemory