Module timing_graph 

A circuit’s timing graph: how deep its logic is, where the depth sits, and the bound its loops put on the clock, known before Quartus runs.

script elaborates a module through yosys the way an FPGA flow sees it, flattened with every cell keeping the instance path it came from: adders, subtractors, negations, comparisons and dividers stay whole, as the carry chains the fabric builds them from; multipliers stay whole, as DSP blocks; a memory read through a clock stays whole, as a block RAM (its read register found once each flip-flop’s enable is its own, so a read held under an enable is the RAM’s; a value cleared to zero stays logic before its register, not a reset pin), and one read without a clock becomes logic; a memory written through more than the two ports a block RAM has (an array cleared by a loop) becomes registers before the memory passes, which compare its ports pair by pair, once the writes to one address (a word’s byte lanes) are one port; everything else becomes yosys’s simple gates. An undefined bit of the source is 0, fixed once the memories are collected and before anything is optimized, so the graph is one circuit the source allows and what super::autopipe::emit writes from it is exactly that circuit.

read maps the gates onto six-input LUTs (super::lutmap, wide AND, OR and XOR trees balanced for LUTs) and turns the netlist into a graph over net bits whose edges carry a delay and a register count, the retiming graph of Leiserson & Saxe:

• a LUT adds Delays::lut from each input to its output, and so does a $lut cell a netlist brings mapped;
• a carry chain enters each bit through a LUT, Delays::lut, and carries Delays::carry from bit to bit; a comparison is the chain’s carry out;
• a divider is the array of subtractions that builds it, one a quotient bit from the top: each stage a LUT and a carry across the divisor, the quotient bit out of its stage and the remainder out of the last;
• a multiplier is a DSP block, Delays::dsp from its operands to its product, unless one operand is a constant power of two, which is wiring;
• a memory holds its contents one register past its write port; a read port with a clock holds one more and adds Delays::memory to its data, and one without adds Delays::memory from its address;
• a flip-flop is an edge from each of its inputs to its output holding one register.

TimingGraph::depth times the combinational edges: the deepest path, and for every instance the deepest path through its own cells and through its subtree, the two figures Quartus prints as an entity’s Max Depth. TimingGraph::endpoints is the deepest path into each register and each output, so a pipeline’s stages are each as deep as the paths into the registers that end them. TimingGraph::loop_bound is the maximum cycle ratio (logicaffeine_proof::cycle_ratio): the clock no retiming of the design can beat, with the loop that sets it, certified.

The model is one clock: every flip-flop counts as a register of the same clock.

A module script is given as a box, or one the source declares (* blackbox *), is timed apart: emptied before the hierarchy is elaborated, nothing under it is ever read, and each instance is a Boxed, every bit it reads the end of the paths into it (End::Box), as an output is, and every bit it drives the start of the paths out of it, as an input is. A shell is so timed around the engine it holds, in seconds; a loop through the box is the box’s to time, and super::autopipe cuts nothing around one.

Structs

Area

What cells take as the timing graph maps them: six-input LUTs, carry-chain bits (a divider’s every stage a chain as wide as its divisor), DSP blocks in halves (dsp_halves), flip-flop bits and memory bits. A black box takes nothing here.

AreaFit

ALUTs from an instance’s Area: scale × (luts + carry × carry bits), fitted to the instances of at least floor ALUTs, error the root mean square of the log of each prediction over Quartus’s count.

Boxed

An instance of a module timed apart, a black box: each bit it reads a node that ends the paths into it, as an output does, and each bit it drives a node that starts the paths out of it, as an input does. None of its own logic is in the graph, nor any loop through it.

CalibratedInstance

An instance both report: its path ("" for the top), Quartus’s Max Depth and the model’s depth, and what it takes as Quartus’s synthesis counted it beside what the model maps it to.

Calibration

The model’s depth and area beside Quartus’s, build by build: what timing_calibrate records, never edited by hand.

CalibrationRow

One synthesis: its Verilog by SHA-256, the delays the model used, and the deepest path through each instance, as Quartus reported it (logic levels) and as the model predicts it (the model’s unit).

Cone

The gates a mapped LUT covers, over its pins: each gate’s operands an earlier gate or a pin, plain or inverted, and the LUT’s output one of them.

ConeArg

A cone operand: pin index, or gate index − pins past the pins; inverted or not.

ConeGate

Cost

What an edge or a path adds, counted by kind: its delay at any Delays is the sum of each count times its delay.

Delays

The delay each kind of cell adds, in a common integer unit.

Depth

How deep a graph’s logic is.

Endpoint

The deepest path into a register or an output, over all its bits.

Fanout

The loads of a graph read from a netlist: what each edge loads the node it starts from with — a cell input one, a memory port the blocks of its RAM it reaches (memory_blocks) — each node’s driver, the most loads its net asks a copy of its driver to take ((* maxfan = N *), as Quartus duplicates a register to keep each copy to N), and which nodes are clocks.

Fitted

Delays fitted to measured depths (fit).

InstanceArea

An instance’s area two ways: Quartus’s synthesis hierarchy, and the timing graph’s Area of its subtree.

InstanceDepth

The deepest path through an instance’s cells.

KeptCell

A cell kept whole (a carry chain, a divider, a DSP product): its kind, its parameters, each port’s bits, and a node inside it whose stage is the cell’s.

QuartusArea

What Quartus’s synthesis hierarchy counts for an instance and everything under it.

RefusedBuild

A synthesis the model could not map: its Verilog by SHA-256 and what refused it (yosys’s error line, or the timing graph’s).

Structure

What a graph was read from, node by node: every node’s source, the kept cells, and the ports by name.

TimingGraph

A timing graph: a node per net bit and per internal point of a carry chain, DSP block or memory.

Wide

A net past its bound: its node and name, the loads it drives and what drives it.

Enums

Driver

What drives a node of a graph read from a netlist.

End

What ends a path: a register, which one clock must reach, an output of the module, or a box’s input.

Pin

A pin’s signal: a node, or a constant.

Source

How the value at a node is made.

TimingError

Why a module has no timing graph.

Constants

AREA_CARRIES

The carry weights fit_area searches against a LUT’s: 0 to 3 in twentieths.

BOX_AREA

The module attribute that says the area each instance of a box takes, as a device block’s stand-in declares it: its Area’s five counts, luts,carry,half_dsps,flops,memory_bits; a box without it takes none.

BOX_OUT

The module attribute that says what a box’s outputs add as they leave it: its Cost’s four counts, lut,carry, dsp,memory; a box without it adds nothing.

STRATIX10_NS_PER_LEVEL

The nanoseconds a level of Delays::STRATIX10 takes: a LUT and the interconnect hop into the next.

Functions

dsp_halves

The halves of a Stratix 10 DSP block an a×b product takes: two products of at most 18×19 share a block, one of at most 27×27 fills it, and a wider one is tiled in 27×27 blocks.

fit

The delays under which each graph’s depth comes nearest its measured depth (in the unit a delay of 100 is one of): of candidates, each scaled by the factor that fits it best. A candidate’s ratios choose every critical path, and a graph’s depth scales with all its delays together, so the best scale is the geometric mean of measure over depth, applied to every delay; the error is the root mean square of each log ratio of prediction to measure. Each graph is left reweighed to the delays fitted. The graphs are read from netlists and loop through no logic without a register; every measure is positive.

fit_area

The area fit of samples (an instance’s area, Quartus’s ALUTs) with at least floor ALUTs: of the carries, the weight under which the log ratios of Quartus’s count over luts + weight × carry spread least, the scale their geometric mean. Small instances are left out: a few LUTs either way is most of them.

memory_blocks

The blocks a memory of width bits by size words takes, across its width and down its depth, in the RAM its ramstyle asks for: an MLAB holds 20 bits by 32 words, an M20K 40 bits by 512, and a memory that asks for registers (logic) is a register a bit, read through four-word multiplexers; one that asks for nothing is an M20K, as Quartus builds it.

modules_numbered

The modules verilog defines whose names are one of prefixes and a number, in order of definition: the family a generator writes one module of per width, to name as boxes.

netlist

The netlist script writes for top of verilog with params set, as yosys JSON.

read

The timing graph of a netlist script mapped.

script

The yosys script that maps top with params set and writes timing.json.

synthesize

Map top of verilog with params set, each module of boxes a box, and read its timing graph.