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synthesize

logicaffeine_compile::codegen_sva::timing_graph

Function synthesize 

Source 
pub fn synthesize(
    verilog: &str,
    top: &str,
    params: &[(&str, &str)],
    boxes: &[(&str, Cost)],
    delays: &Delays,
) -> Result<TimingGraph, TimingError>
Expand description

Map top of verilog with params set, each module of boxes a box, and read its timing graph.