Function emit 

pub fn emit(
    graph: &TimingGraph,
    plan: &Plan,
    module: &str,
    enable: Option<&str>,
) -> Result<String, EmitError>

graph’s logic pipelined by plan as a Verilog module named module: every connection reads its source through as many registers as the plan puts on it, clocked by clk and, when enable names a port, stepping only when it is high. An input of the source with one of those names that no logic reads is that port; one the logic reads is refused.