Struct Devices 

pub struct Devices {

    pub flash: Vec<u8>,
    pub uart: Vec<u8>,
    pub link_out: VecDeque<u8>,
    pub link_in: VecDeque<u8>,
    pub buttons: u64,
    pub leds: u64,
    pub switches: u64,
    pub rtl_md5: [u8; 16],
    pub ddr_ready: bool,
    pub ddr_failed: bool,
    pub cycles: u64,
    pub exit: Option<u64>,
    pub reset: bool,
    /* private fields */
}

The board’s devices, as the model of the system around the hart: memory, the flash behind the streaming port, and every register in REGS with the behaviour its line documents. The RTL SoC is held to these. The bus completes every access the memory map permits (memory_map): a device address no register holds reads as zero and ignores writes.

Fields

flash: Vec<u8>

The flash: the bitstream’s 4 MB, then the boot image.

uart: Vec<u8>

Every byte written to the log UART.

link_out: VecDeque<u8>

Bytes the hart sent into the terminal link.

link_in: VecDeque<u8>

Bytes waiting for the hart from the terminal link.

buttons: u64

leds: u64

switches: u64

rtl_md5: [u8; 16]

The bitstream’s RTL fingerprint.

ddr_ready: bool

Whether the DDR2 has calibrated (and whether it failed to).

ddr_failed: bool

cycles: u64

Clock cycles since reset, as SYS_CYCLES reads them.

exit: Option<u64>

The status the firmware stopped the board with.

reset: bool

The firmware asked the board to restart.

Implementations

impl Devices

pub fn new(rom: &[u8], flash: Vec<u8>, rtl_md5: [u8; 16]) -> Self

The devices at reset, with rom in the boot ROM and flash behind the streaming port.

Trait Implementations

impl Bus for Devices

fn read(&mut self, addr: u64, size: u8) -> Result<u64, BusError>

fn write(&mut self, addr: u64, size: u8, value: u64) -> Result<(), BusError>