Module soc 

The system around the hart on Board B, defined once: the physical memory map, the device registers, how the 128 MB of DDR2 is laid out for the firmware, and the flash image the boot ROM loads. The hart model reads the map as its physical memory attributes, the RTL takes it as parameters (verilog_defines), and the boot ROM and the shim compile against the C header this module writes (c_header) — so no address is ever written twice.

Structs

Board

The whole board: the hart at its reset vector over the devices.

Devices

The board’s devices, as the model of the system around the hart: memory, the flash behind the streaming port, and every register in REGS with the behaviour its line documents. The RTL SoC is held to these. The bus completes every access the memory map permits (memory_map): a device address no register holds reads as zero and ignores writes.

Reg

A device register: its name in the C header and its address.

Enums

Stopped

How a run of the board ended.

Constants

BOOT_WORK_BASE

The boot ROM’s working tables (the inflater’s), in the mapping region: nothing uses it before the compiler runs, and the shim zeroes every page it hands out there.

BUTTONS

CONSTANTS

Every constant the firmware compiles against, by its C name.

DDR

FIRMWARE_BASE

FLASH_SIZE

The flash: the bitstream at 0, the boot image here.

HART_HWCAP

The extensions the compiler sees, as Linux reports them in AT_HWCAP (a bit per extension letter): the hart’s I, M, A and C, and the F and D the shim provides — exactly what qemu-riscv64 reports for the same binary.

HART_HZ

The hart’s clock: the DDR2 controller’s divided clock, which the hart shares.

IMAGE_HEADER_SIZE

IMAGE_MAGIC

The boot image’s header: IMAGE_MAGIC, a version and the header’s size, the RTL fingerprint it was built for, the body’s inflated and compressed lengths, and the sha256 of the compressed body.

IMAGE_OFFSET

IMAGE_VERSION

IO_BASE

Device registers.

IO_SIZE

LINK

MMAP_BASE

MMAP_SIZE

QSPI

RAM_BASE

The DDR2.

RAM_SIZE

REGS

Every device register.

RESET_PC

ROM_BASE

The boot ROM: the hart’s reset vector. Address 0 stays unmapped, so a null pointer faults.

ROM_SIZE

SECTION_ARGS

SECTION_BUNDLE

SECTION_FIRMWARE

SECTION_SHIM

A section of the boot image’s body.

SHIM_BASE

How the DDR2 is laid out once the shim runs: the shim itself, the firmware’s image and heap, the region its anonymous mappings come from, the boot image’s staging area, and the firmware’s stack.

SHIM_SIZE

SOC_ID

SYS_ID: “LOGOSHRT” read as a little-endian word.

SOC_RESET_KEY

The value SYS_RESET takes to restart the board.

SRAM_BASE

Scratch RAM in block RAM: the boot ROM’s stack and data before the DDR2 is calibrated. It never holds code.

SRAM_SIZE

STACK_BASE

STACK_SIZE

STAGING_BASE

STAGING_SIZE

SYS

UART

Functions

c_header

The C header the boot ROM and the shim compile against.

memory_map

The physical memory map the hart enforces.

verilog_defines

The RTL’s view of the same map, as defines the SoC’s Verilog includes (once, however many files include it).