Module hart 

The board’s own CPU: an RV64IMAC hart with machine and user modes, built to run the LOGOS compiler from the board’s DDR2 so the board compiles programs for its fabric engine with no computer attached.

model is the hart’s executable specification and rvc its compressed-instruction decompressor; rtl is the Verilog held to them. soc defines the system around the hart — its memory map, device registers and DDR2 layout — once, for the model, the RTL and the firmware’s C; image is the boot image the flash carries; ddr2 is the DDR2 behind it, as the controller schedules it.

Modules

ddr2

The hart’s main memory: the Nexys A7’s DDR2, a Micron MT47H64M16 (1 Gb, x16, eight banks of 8192 rows of 1024 columns), run by hart_ddr2.v at CK = 125 MHz — the slowest clock the part’s DLL is specified for, and twice the hart’s. One hart clock is a frame: two CK cycles, four data beats, one 64-bit word.

image

The boot image the board’s flash holds after its bitstream: a header the boot ROM checks, then a DEFLATE-compressed body of sections — the shim, the compiler (a static riscv64 Linux ELF), the bundle of LOGOS sources it may open, and, when a run is given them, the compiler’s arguments. The boot ROM refuses an image whose RTL fingerprint is not the bitstream’s, digests the compressed stream as it inflates it, and refuses one whose digest does not match.

model

The executable specification of the hart: an RV64IMAC processor with the Zicsr and Zifencei extensions, machine and user modes and eight physical-memory-protection entries, one architectural step at a time. The hart’s RTL is held to this model instruction by instruction, and this model is held to the RISC-V architecture tests and to qemu-riscv64.

rtl

The hart’s RTL, as Verilog source files the board image and the simulations read. The hart is held to super::model (and its decompressor to super::rvc) by hart_rtl_lock; the computer around it, to the board model super::soc::Board by hart_soc_lock; the DDR2 controller, to the part’s data sheet by hart_ddr2_lock.

rvc

The RV64C decompressor: every 16-bit instruction is a shorthand for one 32-bit instruction, and the hart executes the expansion. expand returns that 32-bit instruction, or None for an encoding the C extension reserves (an illegal instruction). HINT encodings expand to the base instruction whose destination is x0 or whose effect is nil, as the specification defines them. The hart’s RTL expander is held to this function over all 65,536 encodings, and this function is held to the GNU disassembler.

soc

The system around the hart on Board B, defined once: the physical memory map, the device registers, how the 128 MB of DDR2 is laid out for the firmware, and the flash image the boot ROM loads. The hart model reads the map as its physical memory attributes, the RTL takes it as parameters (verilog_defines), and the boot ROM and the shim compile against the C header this module writes (c_header) — so no address is ever written twice.