Struct CoreClock 

pub struct CoreClock {
    pub mult: u32,
    pub div: u32,
    pub out: u32,
}

A board image’s core clock: the 100 MHz oscillator through a PLLE2, its VCO at 100 · mult / div MHz and the core at the VCO over out.

Fields

mult: u32

div: u32

out: u32

Implementations

impl CoreClock

pub const UNCERTAINTY_NS: f64 = 0.5

The core clock’s own allowance a route does not model: the PLL’s output jitter and the clock tree’s skew.

pub fn vco_mhz(self) -> f64

pub fn mhz(self) -> f64

pub fn legal(self) -> bool

Whether a PLLE2 of a speed grade -1 Artix-7 takes these settings (DS181): a multiplier of 2–64, an input divider of 1–56 and an output divider of 1–128, the phase detector at 19–450 MHz and the VCO at 800–1600 MHz.

pub fn fastest_within(period_ns: f64) -> Option<CoreClock>

The fastest legal core clock whose period is at least period_ns; of clocks as fast, the one with the smallest input divider, then the slowest VCO.

pub fn for_route(fmax_mhz: f64, residual_ns: f64) -> Option<CoreClock>

The fastest legal core clock a route closes under the clock contract: its period at least the routed path (1000 / fmax_mhz), the residual the router bounds but does not time (residual_ns) and Self::UNCERTAINTY_NS.

Trait Implementations

impl Clone for CoreClock

fn clone(&self) -> CoreClock

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for CoreClock

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl PartialEq for CoreClock

fn eq(&self, other: &CoreClock) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for CoreClock

impl Eq for CoreClock

impl StructuralPartialEq for CoreClock