Module fabric_board 

A fabric decode step as a board image: the step’s RTL behind its host port, a serial line in front of the port, and the autoregressive loop run on chip.

The image serves a byte protocol over 8N1 serial, every multi-byte field little-endian:

Command	Arguments	Reply
I identify	—	i, L O G S, the memory read latency
W write a word	tensor (2), word (4), value (8)	k
R read a word	tensor (2), word (4)	r, value (8)
S one step	token (2), position (2)	s, next token (2), the step’s cycles (4)
G generate	count (2)	the next token (2) per step, then e and the cycles of the whole loop (4)

A step writes the token and the position into the step’s tensors, resets and starts the fabric, waits for it, and reads the next token back; the cache the step writes stays in its memories. After a step the board holds the token it produced and the position after it, so G continues from the last S: it runs the steps itself, each one’s token the one before it produced and its position the next, and its cycles are the chip’s own decode time (generate_cycles) — the serial line carries two bytes per token and never stalls it while its queue has room. Tokens and positions are the values the step’s tensors hold (the program’s 1-based ones).

Structs

CoreClock

A board image’s core clock: the 100 MHz oscillator through a PLLE2, its VCO at 100 · mult / div MHz and the core at the VCO over out.

DecodeWords

Where a decode step’s token, position and next token live: each a tensor and the word of its element (0, 0).

Enums

BoardImageError

Why a program has no board image.

BoardProtocol

The protocol a board image serves over its byte channel: the decode step’s (decode_board: I, W, R, S, G) or a chip’s of a program split over chips (chip_board: I, W, R, X).

ImageRole

What a board image runs: a whole decode step, which the host steps and the chip loops (BoardProtocol::Decode), or one chip’s program of a split, which the host runs from halt to halt (BoardProtocol::Chip).

NexysBoard

A Nexys board the image is built for.

Constants

FT245_UART_BRIDGE_V

The FT245 bridge a Nexys Video top instantiates: the board’s FT245 FIFO to a serial pair. benchmarks/silicon/ft245_uart_bridge.v is its golden twin, for the board flows that read it there.

Functions

board_image

Every file a board build reads, by name: the program’s RTL and the memory images its $readmemh loads, protocol’s module with the serial pair, the board’s top — named top, its core at clock — its constraints, and the hand-written Verilog the top instantiates (NexysBoard::extra_sources).

chip_board_verilog

chip_board: one chip’s program of a program split over chips (compile_program_to_chips), its host port and its halts driven over the serial pair. Beside I, W and R as decode_board serves them:

chip_record

What a host needs of one chip’s program of a program split over chips, as its ledger states it: the twin’s count at each halt and at the end (fabric_cycle_segments), each link — the section it follows, whether the fabric halts there, and each tensor it sends and receives with its id and every element’s host word, row-major — the words of the step’s inputs (tok, pos) the chip holds, and of its result (next) if it holds it. None where the fabric does not lower p.

clks_per_bit

The serial line’s bit time in core clocks at 115200 baud.

decode_board_verilog

decode_board: the step (spatial_top), its host port driven by the protocol, the serial pair and a 128-byte reply queue. lat is the step’s memory read latency, the cycles a host read waits for its word.

generate_cycles

The cycles G reports for steps that took step_cycles each: per step, the protocol’s thirteen states around the step — G_LOOP, the token and position writes, the reset, the start, the cycle the fabric’s count ends on, the next token’s read and its lat cycles, G_TOK, and the four that queue the token’s two bytes. The G_LOOP that finds no step left reports the count as it stands before that cycle.

image_digest

The identity of a board build: the sha256, in hex, of every file synthesis reads — in name order, each its name, a zero byte, its text and a zero byte — with every Verilog file’s simulation-only regions (synthesis translate_off through synthesis translate_on) taken out, so a check only a simulation runs moves no bitstream’s identity.

program_board_image

The board image of p, a fabric program for target: lowered, its memories loaded with its fills, on board with the top named top and its core at clock, speaking role’s protocol (a decode step’s through its tok, pos and next words). Every file synthesis reads, so its image_digest is the image’s identity.

relay_record

The relay as a split ledger states it: {"run": chip, "to": link} and {"copy": tensor, "from": chip, "to": chip}.

synthesized

verilog as synthesis reads it: without its simulation-only regions.

uart_verilog

An 8N1 receiver and transmitter: the receiver samples each bit at its middle and raises valid for one cycle with a byte whose stop bit held; the transmitter sends data when go is raised while it is idle.