pub fn board_image(
art: &VerilogArtifact,
images: &[(String, String)],
protocol: BoardProtocol,
lat: u64,
board: NexysBoard,
top: &str,
clock: CoreClock,
) -> Vec<(String, String)>Expand description
Every file a board build reads, by name: the program’s RTL and the memory images its $readmemh loads, protocol’s
module with the serial pair, the board’s top — named top, its core at clock — its constraints, and the
hand-written Verilog the top instantiates (NexysBoard::extra_sources).