Enum NexysBoard 

pub enum NexysBoard {
    A7,
    Video,
}

A Nexys board the image is built for.

Variants

A7

The Nexys A7-100T (XC7A100T-1CSG324C): its byte channel is the FT2232’s UART bridge.

Video

The Nexys Video (XC7A200T-1SBG484C): its byte channel is the FT2232’s FT245 FIFO, which the FT245 bridge (FT245_UART_BRIDGE_V) turns into the serial line decode_board speaks.

Implementations

impl NexysBoard

pub fn part(self) -> &'static str

The part, as the open flow names it.

pub fn extra_sources(self) -> &'static [(&'static str, &'static str)]

The hand-written Verilog the top instantiates beside the step and its protocol, each by its file name and text.

pub fn top_verilog( self, top: &str, clock: CoreClock, protocol: BoardProtocol, ) -> String

The board’s top top: the 100 MHz oscillator through a PLL onto a global clock buffer for the core at clock, a reset held until the PLL locks and eight cycles after, protocol’s module on the board’s byte channel, and the eight status LEDs.

pub fn xdc(self, top: &str, protocol: BoardProtocol) -> String

The constraints for top: the oscillator, the byte channel’s pins and the LEDs, from Digilent’s master XDC files.

Trait Implementations

impl Clone for NexysBoard

fn clone(&self) -> NexysBoard

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for NexysBoard

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl PartialEq for NexysBoard

fn eq(&self, other: &NexysBoard) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for NexysBoard

impl Eq for NexysBoard

impl StructuralPartialEq for NexysBoard