Function fp32_verilog 

pub fn fp32_verilog() -> &'static str

logos_fmul(a, b) -> y and logos_fadd(a, b) -> y, and their pipelined copies logos_fmul_p (three registered stages) and logos_fadd_p (four), a pair of operands a clock, each the same function of the operands its latency before; logos_tree16, the pairwise tree of sixteen lanes’ sums (crate::spatial::decode_engine::numerics::fdot’s fold), and its pipelined copy logos_tree16_p on logos_fadd_p, sixteen lanes a clock; and the binary16 codec logos_f32_to_f16 and logos_f16_to_f32 (crate::spatial::decode_engine::numerics::f32_to_f16, crate::model::quant::f16_to_f32): nearest even, binary16 denormals kept, an f32 denormal a zero of its sign, past the top infinite; and the rounding’s pipelined copy logos_f32_to_f16_p (F32_TO_F16_LATENCY).