Module decode_engine 

The LOGOS decode engine: a spatial dataflow on one card that holds its sequences’ token-rows on chip and streams the weights through them once a pass.

numerics is the engine’s arithmetic, bit for bit: what every unit computes, so the hardware is held to it exactly and it is held to the model’s own arithmetic within a measured bar. model runs a checkpoint in it. lane is the block-scale lane over the integer sums the array actually delivers; vector is the vector unit’s instruction set and the micro-programs it runs; program is a checkpoint’s step as the commands the units run, the list model interprets; machine runs it as the jobs the sequencer issues over the card’s memory, every byte where it lives; twin prices a program command by command on the engine’s units; rtl prints the units; ofs writes the D5005’s accelerator build tree around them. image lays a checkpoint’s weights over the card’s memory channels in the order a pass reads them; physical places the rest of a machine’s memory over the channels and names the streams of each sequence’s state; ddr prices a pass’s streams on those channels.

Modules

capability

What the decode engine runs: a checkpoint held, feature by feature and tensor by tensor, to the program super::program::lower reads off the model’s one program and the units compute, and every gap refused by name.

ddr

The engine’s memory traffic on the card’s DDR4 channels: what the controller model (crate::codegen_sva::ddr4_jedec) makes of each kind of stream a pass issues, at the card’s own timing.

image

The weight image: a checkpoint’s tensors laid out over the card’s memory channels in the order a pass reads them, so each channel streams its share of every pass as one run of lines.

lane

The block-scale lane: a weight block’s integer sums as the array and the activation side deliver them, turned into the block’s f32 value and added into its row, exactly as super::numerics::dot does under ActScaling::PerBlock.

lower_graph

The engine’s program read off a model’s step graph: the decode step crate::model::author::decode_step writes for a ModelSpec, lifted into the one IR and fused by the shared table under the engine’s shim (super::shim::EngineShim), read block by block into the Commands of super::program.

machine

The decode engine’s machine: a step as the jobs its sequencer runs over the card’s memory, every byte where it lives.

model

The decode engine’s model: a hybrid Gated-DeltaNet checkpoint (qwen35, Qwen3.5 and Qwen3.8) run over a batch of sequences in the engine’s arithmetic, every number from super::numerics.

numerics

The decode engine’s arithmetic, bit for bit.

ofs

The decode engine as an accelerator function of the Open FPGA Stack on the Intel PAC D5005.

physical

The card’s memory as its four channels hold it: where every byte of a machine layout (super::machine::Layout) lives, and the streams a job’s reads and writes of one sequence’s state are on each channel.

program

The decode engine’s program: one step of a checkpoint as the commands its units run, in order.

rtl

The decode engine’s units as Verilog, each computing exactly what its super::numerics function computes.

shim

What the decode engine runs as one unit: its answer to the shared optimizer.

twin

The decode engine’s cycle twin: a step’s program priced command by command on the engine’s units.

vector

The vector unit’s instruction set: sixteen f32 lanes over vector and scalar registers, every instruction one of the engine’s f32 operations in the order super::numerics defines it, so a micro-program computes what the numerics function it is written from computes, bit for bit.