Module ddr 

The engine’s memory traffic on the card’s DDR4 channels: what the controller model (crate::codegen_sva::ddr4_jedec) makes of each kind of stream a pass issues, at the card’s own timing.

A pass streams three kinds of lines through a channel. The weights are one long read of the channel’s share of the weight image. A Gated-DeltaNet memory, rewritten every pass, is read and written back in place a chunk at a time, the chunk being what the recurrence unit holds between its read and its write. An attention block’s cache is one long read of a sequence’s positions and an append of the new one after them. ddr_ledger prices each on one channel, the state and cache bytes from the decode pricer’s own accounting of Qwen3.8-27B’s header (an f16 memory and conv ring, an int8 cache), at both of the engine’s beats, four sequences back to back so the turns between them are paid; every trace is held to JESD79-4 as it is issued.

Structs

DdrLedger

The ledger: the channel’s clocked rules, the controller model’s queue, the bytes the streams are sized from, and every stream’s price.

DdrRow

One stream priced on one channel.

Constants

CACHE_POSITIONS

Positions a sequence’s cache holds when it is read.

HEADER

The checkpoint whose state and cache the ledger streams.

SEQUENCES

Sequences each state and cache row streams back to back.

STATE_CHUNKS

Lines the recurrence unit reads before it writes them back.

WEIGHT_LINES

Lines of the weight stream priced: long enough to pay its refreshes as a whole pass does.

Functions

ddr_ledger

Every stream of a pass priced on one D5005 channel.

stream_bytes

One sequence’s state and one position of its cache, from the decode pricer’s stages of h with an f16 state and an int8 cache.