Module wpe_offchip 

The whole-program engine with its bulk memories off the die: the same loader and interpret FSM, whose heap, frame stack and config image — any of them — live in a QSPI PSRAM behind one psram_edge, each through its own psram_cache, the caches sharing the edge through a psram_arbiter.

Every cache keeps the port of the block RAM it replaces — a registered read one cycle after its address, refreshed every cycle — and while any of them serves a miss it raises mstall, which freezes the whole loader/interpret FSM. A program’s Show records, its result and its counted run cycles are therefore the on-chip engine’s exactly; a miss costs only wall-clock time. The one input that does not wait is the UART: the receiver holds one byte while the FSM is stalled, so no byte is lost as long as every stall the loader can meet is shorter than a byte (OffchipMemory::check_uart).

The memories an engine sends off-chip are named by the floorplan’s own ArrayRoles, so the plan that decides what leaves the die (plan_wpe) and the RTL that takes it away speak one vocabulary.

Structs

OffchipMemory

The engine memories behind one PSRAM edge, each with its own cache; None keeps a memory on the die.

Region

One memory’s place in the part: a naturally aligned power-of-two block of words at base, so its address is the region’s high bits over the low bits bits of its own index.

Enums

OffchipUnplaceable

Why an engine cannot have these memories off-chip.

Functions

emit_wprog_engine_soc_offchip_testbench

The over-the-wire host for the off-chip engine, on a board carrying the part: the same stimulus and checks as the on-chip testbench, the clock at the edge’s system period, the part’s pin model on the SIO pads, and a monitor that fails the run the moment a received byte is overwritten before the engine takes it. Prints a FRAME line per program, then PSRAM-VIOLATIONS and PSRAM-STALL-CYCLES.

emit_wprog_engine_soc_offchip_testbench_clocked

emit_wprog_engine_soc_offchip_testbench with the clock at clk_period_ps — any period in the edge’s clock range, where its cycle counts meet every timing of the part.

emit_wprog_engine_soc_verilog_offchip

The engine with memory’s memories off the die: the template’s off-chip regions for each of them and the generated glue, then the FPU modules, the cache, the arbiter and the edge, in one file.

uart_byte_cycles

System cycles of one UART byte at clks_per_bit: a start bit, eight data bits and a stop bit.

wire_bytes_before_first_part_access

The fewest bytes the loader takes before it can touch the part. A program whose every config memory and parameter list is empty streams exactly these, ending in the go byte that starts the heap clear; every other stream writes its first cell, its first preloaded word or its heap later still.