Function wpe_caravel_memory 

pub fn wpe_caravel_memory() -> OffchipMemory

The shipped off-chip memories: the edge’s cycle counts are timed at 16 ns with two engine cycles per SCLK half (a 64 ns SCLK), so every slower clock meets tPU, tRST, tCPH, tCLK and tACLK too, and its bursts are cut for 40 ns, where tCEM leaves two words a line; heap, frame stack and config image each get eight such lines.