logicaffeine_compile/codegen_sva/hart/mod.rs
1//! The board's own CPU: an RV64IMAC hart with machine and user modes, built to run the LOGOS compiler from the board's
2//! DDR2 so the board compiles programs for its fabric engine with no computer attached.
3//!
4//! [`model`] is the hart's executable specification and [`rvc`] its compressed-instruction decompressor; [`rtl`] is the
5//! Verilog held to them. [`soc`] defines the system around the hart — its memory map, device registers and DDR2
6//! layout — once, for the model, the RTL and the firmware's C; [`image`] is the boot image the flash carries; [`ddr2`]
7//! is the DDR2 behind it, as the controller schedules it.
8
9pub mod ddr2;
10pub mod image;
11pub mod model;
12pub mod rtl;
13pub mod rvc;
14pub mod soc;