pub struct Schedule {
pub rcd: u64,
pub ccd: u64,
pub read_done: u64,
pub write_done: u64,
pub rfc: u64,
pub refi: u64,
pub power_up: u64,
pub cke_settle: u64,
pub mrd: u64,
pub dllk: u64,
}Expand description
The controller’s schedule, in frames: what verilog_params hands hart_ddr2.v. A line transaction issues
ACTIVATE at frame 0 and its four column commands at cas(k); the write data’s DQS preamble is the frame after a
WRITE and its eight beats the two frames after that (WL = CL − 1 = four CK cycles); the bank is idle and every
constraint met by read_done / write_done.
Fields§
§rcd: u64§ccd: u64§read_done: u64§write_done: u64§rfc: u64§refi: u64§power_up: u64§cke_settle: u64§mrd: u64§dllk: u64Implementations§
Trait Implementations§
impl Copy for Schedule
impl Eq for Schedule
impl StructuralPartialEq for Schedule
Auto Trait Implementations§
impl Freeze for Schedule
impl RefUnwindSafe for Schedule
impl Send for Schedule
impl Sync for Schedule
impl Unpin for Schedule
impl UnsafeUnpin for Schedule
impl UnwindSafe for Schedule
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