Module ddr2 

The hart’s main memory: the Nexys A7’s DDR2, a Micron MT47H64M16 (1 Gb, x16, eight banks of 8192 rows of 1024 columns), run by hart_ddr2.v at CK = 125 MHz — the slowest clock the part’s DLL is specified for, and twice the hart’s. One hart clock is a frame: two CK cycles, four data beats, one 64-bit word.

The controller moves whole 64-byte lines, closed-page: ACTIVATE, four BL8 bursts two frames apart (the last with auto-precharge), and the bank idle again before the next line. Every command is in a frame’s first CK cycle. This module is the one definition of the part’s timing, the frame counts the controller schedules by, the mode registers, the power-up sequence, the address map and the calibration pattern; hart_ddr2.v takes them through verilog_params, and the simulation’s device model checks the controller against the part’s own numbers.

Structs

Part

The part’s timing, from the MT47H64M16 data sheet (-25E grade), in picoseconds unless named in CK cycles.

Schedule

The controller’s schedule, in frames: what verilog_params hands hart_ddr2.v. A line transaction issues ACTIVATE at frame 0 and its four column commands at cas(k); the write data’s DQS preamble is the frame after a WRITE and its eight beats the two frames after that (WL = CL − 1 = four CK cycles); the bank is idle and every constraint met by read_done / write_done.

Constants

BURSTS_PER_LINE

BURST_BEATS

Burst length, in beats (BL8): sixteen bytes, two frames.

CK_PS

One CK cycle, and one frame (a hart clock), in picoseconds.

FRAME_PS

MT47H64M16

Functions

calibration_line

The line the controller writes and reads back to calibrate its read capture: thirty-two beats per byte lane, each byte distinct within its lane and from every other’s complement, so the first beat (or its complement) is found at exactly one place in the captured stream and the rest confirm it.

cks

CK cycles covering at least ps.

emr1

Extended mode register 1: DLL on, full drive, no on-die termination, no additive latency, differential DQS; the off-chip driver calibration as given (0b111 default, 0 exit).

frames

Frames covering at least ps.

init_sequence

The JEDEC power-up sequence in frames.

init_word

An init step as the controller’s ROM word: {cke, cs_n, ras_n, cas_n, we_n, ba[2:0], a[12:0], frames[23:0]} (45 bits), the command’s pins from the JEDEC truth table ddr2_pins.

locate

Where a byte of the RAM lives: (row, bank, column). The bank bits sit just above a row’s 2 KB, so consecutive rows of the address space rotate through the banks.

mr

The mode register: BL8, sequential, CAS latency, write recovery, and whether the DLL resets.

schedule

verilog_params

The parameters hart_ddr2.v includes (hart_ddr2_params.vh): the schedule in frames, the power-up ROM, the calibration line.