Struct FabricTarget 

pub struct FabricTarget {

    pub name: &'static str,
    pub rows: usize,
    pub cols: usize,
    pub width: u32,
    pub alu_ops: BTreeSet<AluOp>,
    pub func_units: BTreeSet<FuncUnit>,
    pub mem_depth: usize,
    pub agu: bool,
    pub simd: Option<LaneTy>,
    pub dataflows: BTreeSet<Dataflow>,
    pub precisions: BTreeSet<Precision>,
    pub mem: MemHierarchy,
    pub fusion_window: usize,
    pub silicon: Option<SiliconSpec>,
    pub metapipeline_depth: usize,
    pub banks: usize,
    pub counter_nest: usize,
}

A described fabric — the ADL. One certified lowering (place_with_target) retargets across shapes by varying this descriptor; each setting is either provably ≡VM or refused with an Unplaceable.

Fields

name: &'static str

Human name (carried into refusal errors).

rows: usize

Described array dimensions.

cols: usize

width: u32

Datapath bit width (metadata for the reconfig/SIMD proofs; the SAT proof width is separate).

alu_ops: BTreeSet<AluOp>

The combinational ALU ops this target provides.

func_units: BTreeSet<FuncUnit>

The sequential functional units this target provides.

mem_depth: usize

Heap depth in words; 0 means no state plane (memory cells are refused).

agu: bool

Whether the target carries a decoupled address-generation unit (Phase 1).

simd: Option<LaneTy>

The packed-SIMD lane configuration this target provides, if any (Phase 2). None ⇒ scalar-only.

dataflows: BTreeSet<Dataflow>

The GEMM dataflow modes this target realizes — always includes Dataflow::Reduction (the baseline).

precisions: BTreeSet<Precision>

The numeric MAC formats this target realizes (the precision dial).

mem: MemHierarchy

The memory hierarchy this target provides (on-chip SRAM / HBM / DDR).

fusion_window: usize

How many ops the target fuses into one spatial pipeline stage (1 = no cross-op fusion).

silicon: Option<SiliconSpec>

Real-chip metadata (compute/memory tiles, node, roofline) for a physically-backed target; None for the abstract presets. Cited to public sources at the constructor.

metapipeline_depth: usize

Pipelined compute stages between buffers the target sustains (1 = a single combinational stage).

banks: usize

Scratchpad banks a memory unit serves concurrently (1 = a flat single-port heap).

counter_nest: usize

Loop-nest depth the target’s own control (counter chain) drives without a CPU (1 = one loop).

Implementations

impl FabricTarget

pub fn full(rows: usize, cols: usize, width: u32) -> FabricTarget

The superset target: every ALU op + every functional unit + a heap. The “can place anything that fits” shape used to certify the placer without capability refusals getting in the way.

pub fn with_alu_ops( name: &'static str, rows: usize, cols: usize, width: u32, ops: &[AluOp], ) -> FabricTarget

An ALU-only target with exactly the given op set — no functional units, no heap. For refusal tests and minimal wearable-class arrays.

pub fn tiny() -> FabricTarget

TINY — a pure combinational scalar array: full ALU, no functional units, no state plane. The smallest useful knob (branchless arithmetic kernels only).

pub fn wearable() -> FabricTarget

WEARABLE — the realistic edge target: full ALU + every functional unit (division + the float lane) + a heap + a decoupled AGU. The HiVec-class knob these levers were built for.

pub fn wide() -> FabricTarget

WIDE — the superset knob: everything the fabric can place, on a large array. Nothing is refused for lack of capability (only for lack of room).

pub fn rdu_shaped() -> FabricTarget

RDU-SHAPED — a descriptor modeling the SambaNova SN40L RDU, from published specs. The PCU is configurable as a weight-stationary / output-stationary systolic GEMM OR a SIMD-elementwise pipeline (both dataflows + reduction), fed by a three-tier SRAM/HBM/DDR hierarchy (PMU scratchpad + package memory) with deep operator fusion. Our certified lowering places onto THIS shape — the pitch target.

Public SN40L specs (each pinned by sn40l_target_lock):

• 1040 PCUs + 1040 PMUs, TSMC 5 nm, 10.2 bf16 PFLOPS roofline → SiliconSpec.
• Three-tier memory: 520 MiB on-chip SRAM, 64 GiB co-packaged HBM, 1.5 TiB DDR.
• Datatypes BF16 / FP32 / INT32 / INT8; we advertise only the precisions our fabric places AND witnesses (Int8 + Bf16). FP32/INT32 are chip-supported but witness-pending — NOT gated as available, to keep the precision ratchet honest. Sources: SambaNova Hot Chips 2024 (hc2024.hotchips.org) · arXiv 2405.07518 · ServeTheHome · sambanova.ai.

(rows, cols) models the placement envelope of ONE datapath, not the 1040-PCU mesh (that is silicon.compute_tiles); the per-PCU systolic dimension is not public.

Derived from RduChipFacts::sn40l: the published numbers above live there with their citations, and the per-PCU pipeline depth / PMU banking / counter chain — not public — come from the facts’ unit model, labeled modeled and cited to the open RDU (Plasticine, ISCA 2017) they are inherited from.

pub fn sn50_shaped() -> FabricTarget

SN50-SHAPED — the SambaNova SN50 RDU, derived from RduChipFacts::sn50: the same PCU capability envelope as the SN40L (systolic + SIMD dataflows, the three memory tiers, a decoupled AGU, deep fusion), with the SN50’s published memory — 432 MB on-chip SRAM, 64 GB HBM2E, DDR5 up to 512 GB — and a 1.6 bf16 PFLOPS per-RDU roofline at TSMC 5 nm. The PCU/PMU counts are not public and are inherited from the SN40L (modeled, so labeled on the mesh descriptor). Only the witnessed precisions (int8 + bf16) are advertised; the chip’s FP8 and FP32 are witness-pending and refused by name until their witness ships.

pub fn plasticine_shaped() -> FabricTarget

PLASTICINE — the open RDU: Prabhakar et al., Plasticine: A Reconfigurable Architecture for Parallel Patterns, ISCA 2017 (DOI 10.1145/3079856.3080256). A 16×8 checkerboard of 64 PCUs + 64 PMUs at 28 nm (112.8 mm², 49 W, 1 GHz, 12.3 fp32 TFLOPS, 16 MB scratchpad). A PCU is a 6-stage × 16-lane SIMD pipeline of 32-bit FUs (integer + fp32) with a cross-lane reduction tree and a counter chain; a PMU is a 16-bank × 16 KB = 256 KB scratchpad with an address-calculation datapath (strided / FIFO / line-buffer / duplication banking, N-buffering). Interconnect: statically configured scalar / vector / control networks. Off-chip: 4 DDR3-1600 channels, 51.2 GB/s (bandwidth on the mesh descriptor, super::plasticine::PlasticineTarget; DRAM capacity is unpublished, so no ddr_gib is claimed).

Capability envelope, honestly: the PCU realizes Reduction (SIMD lanes + tree) — it is NOT a systolic array, so weight-/output-stationary modes are refused; the FUs are 32-bit, so the only advertised precision is the witnessed fp32 (no int8/bf16 MAC exists). (rows, cols) = one PCU datapath envelope (stages × lanes); the mesh lives on silicon + the mesh descriptor. Peak bf16 is 0: the chip has no bf16 datapath.

pub fn provides(&self, cap: Capability) -> bool

Whether this target provides a required capability.

pub fn require_cells(&self, cells: &[LoopCell]) -> Result<(), Unplaceable>

The capability half of place_with_target: every cell’s required capability is provided, or the FIRST missing one is named. A program larger than one datapath envelope (a whole decision program spanning many PCUs) is gated here cell by cell; its geometry is the mesh’s question.

pub fn require_gemm( &self, dataflow: Dataflow, precision: Precision, ) -> Result<(), Unplaceable>

Gate a requested (dataflow, precision) GEMM against this target — the check Phase-1+ lowerings call before placing a systolic/precision datapath. Returns a typed Unplaceable::MissingCapability naming the FIRST dial the target lacks (dataflow before precision), or Ok(()) if both are provided.

Trait Implementations

impl Clone for FabricTarget

fn clone(&self) -> FabricTarget

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for FabricTarget

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl PartialEq for FabricTarget

fn eq(&self, other: &FabricTarget) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Serialize for FabricTarget

fn serialize<__S>(&self, __serializer: __S) -> Result<__S::Ok, __S::Error>

where __S: Serializer,

Serialize this value into the given Serde serializer.

impl StructuralPartialEq for FabricTarget