Enum LoopCell 

pub enum LoopCell {
    Arith {
        op: AluOp,
        a: Src,
        b: Src,
    },
    Select {
        cmp: CmpKind,
        ca: Src,
        cb: Src,
        t: Src,
        e: Src,
    },
    Func {
        unit: FuncUnit,
        a: Src,
        b: Src,
    },
    MemRead {
        addr: Src,
    },
    HeapRead {
        addr: Src,
    },
    HeapWrite {
        addr: Src,
        val: Src,
    },
    HeapAlloc {
        size: Src,
    },
    VectorArith {
        op: VecOp,
        ty: LaneTy,
        a: Src,
        b: Src,
    },
}

One body cell of the CGRA fabric: an arithmetic tile, or a predicated SELECT (mux) tile whose comparison is folded in. A branch in the loop body is if-CONVERTED to a Select: both arms compute, the signed predicate selects — control becomes data, no divergence.

Variants

Arith

v = a op b.

Fields

op: AluOp

a: Src

b: Src

Select

v = (ca cmp cb) ? t : e — the CGRA mux tile, the predicate folded in.

Fields

cmp: CmpKind

ca: Src

cb: Src

t: Src

e: Src

Func

v = a unit b — a SEQUENTIAL functional-unit tile (signed division/remainder via the shared_divider). Distinct from Arith so the emitter wires the multi-cycle divider, not a combinational one. See FuncUnit.

Fields

unit: FuncUnit

a: Src

b: Src

MemRead

v = seq[addr] — a MEMORY-read tile reading the loop’s iterated sequence (see LoopFabric::seq_input) at addr (the induction variable). On silicon this is a scratchpad read (the induction counter drives the address bus); in the model it indexes the sequence array.

Fields

addr: Src

HeapRead

v = heap[addr] — a HEAP-read tile (the shared state plane). The heap mirrors the VM’s exact layout: a collection at pointer p is heap[p] = length then its elements at heap[p+1..=p+len] (1-based). length of xs is HeapRead(p); item i of xs is HeapRead(p + i). This is the collection-read primitive the whole state plane composes from (with HeapWrite/HeapAlloc).

Fields

addr: Src

HeapWrite

heap[addr] = val (side effect); the tile’s value is val. SetIndex/ListPush compose from this.

Fields

addr: Src

val: Src

HeapAlloc

Allocate size fresh words at the heap top (zeroed); the tile’s value is the NEW pointer. NewList composes an alloc + writes; value semantics (COW) are handled upstream by DeepClone/EnsureOwned.

Fields

size: Src

VectorArith

A packed-SIMD tile: a VecOp (lane-wise add / bitwise) over two operand words for lane type ty. First-class placeable — routes to a CellKind::Simd tile exactly like Arith; combinational; proven ≡ N independent scalar ops by simd_tile_lock (SAT carry-isolation) + iverilog.

Fields

op: VecOp

ty: LaneTy

a: Src

b: Src

Trait Implementations

impl Clone for LoopCell

fn clone(&self) -> LoopCell

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for LoopCell

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl<'de> Deserialize<'de> for LoopCell

fn deserialize<__D>(__deserializer: __D) -> Result<Self, __D::Error>

where __D: Deserializer<'de>,

Deserialize this value from the given Serde deserializer.

impl Hash for LoopCell

fn hash<__H: Hasher>(&self, state: &mut __H)

Feeds this value into the given Hasher.

fn hash_slice<H>(data: &[Self], state: &mut H)

where H: Hasher, Self: Sized,

Feeds a slice of this type into the given Hasher.

impl PartialEq for LoopCell

fn eq(&self, other: &LoopCell) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Serialize for LoopCell

fn serialize<__S>(&self, __serializer: __S) -> Result<__S::Ok, __S::Error>

where __S: Serializer,

Serialize this value into the given Serde serializer.

impl Copy for LoopCell

impl Eq for LoopCell

impl StructuralPartialEq for LoopCell