Struct DramTimings 

pub struct DramTimings {

    pub banks: u32,
    pub row_bytes: u64,
    pub burst_bytes: u64,
    pub data_cycles: u64,
    pub trcd: u64,
    pub trp: u64,
    pub tras: u64,
    pub trc: u64,
    pub trrd: u64,
    pub tfaw: u64,
    pub tccd: u64,
    pub trfc_pb: u64,
    pub trefi_pb: u64,
    pub twr: u64,
    pub tturn: u64,
    pub hot: bool,
}

LPDDR5X-class timing parameters, in CONTROLLER CLOCK CYCLES, plus geometry. Values are engineering-realistic for an LPDDR5X-6400-class part driven by a controller clock where one RD/WR burst (BL16) occupies data_cycles on the bus — the table is DATA for the memory architect to correct, and every measurement in this module re-derives from it.

Fields

banks: u32

row_bytes: u64

Row (page) size in bytes.

burst_bytes: u64

Bytes transferred by one RD/WR burst.

data_cycles: u64

Cycles one burst occupies the data bus.

trcd: u64

ACT → RD/WR to the same bank.

trp: u64

PRE → ACT to the same bank.

tras: u64

ACT → PRE minimum to the same bank.

trc: u64

ACT → ACT to the same bank.

trrd: u64

ACT → ACT to DIFFERENT banks.

tfaw: u64

Rolling window in which at most four ACTs may issue.

tccd: u64

CAS → CAS (any bank) — data-bus burst spacing.

trfc_pb: u64

Per-bank refresh (REFpb) duration: REFpb → next ACT to that bank.

trefi_pb: u64

Per-bank refresh interval: every bank needs one REFpb per window this long.

twr: u64

Write recovery: last WRITE burst end → PRE on that bank.

tturn: u64

Data-bus turnaround bubble when switching read↔write direction.

hot: bool

Above 85 °C the refresh interval halves.

Implementations

impl DramTimings

pub fn lpddr5x() -> Self

An LPDDR5X-6400-class nominal-corner timing table (16 banks, 2 KB rows, BL16 ≈ 32 B bursts). The t* counts below are JEDEC LPDDR5X typical timings for that speed grade, expressed in the controller’s tick unit — a representative nominal corner, NOT a datasheet pin for a specific die. Validate them against the exact part’s datasheet before production.

pub fn ddr2_micron() -> Self

Micron MT47H64M16 (1 Gb, x16, 8 banks) at DDR2-800 (-25E speed grade, tCK = 2.5 ns), JEDEC 5-5-5 timings expressed in DDR-clock cycles. This is the on-board DRAM of the Nexys A7-100T and the timing FLOOR the ComputeDRAM streams deliberately violate. NOTE: DDR2 has all-bank AUTO-REFRESH only (no per-bank REFpb); the RefPb schema here models refresh as per-bank for schedule/checker compatibility — flagged, and irrelevant to the ACT-PRE-ACT compute path this campaign exercises.

pub fn trefi_effective(&self) -> u64

Trait Implementations

impl Clone for DramTimings

fn clone(&self) -> DramTimings

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for DramTimings

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.