Module dram 

dram — the DRAM machine.

The handout claims “>90% bus efficiency, because the compiler schedules row hits and interleaves banks deterministically” and “refresh is co-scheduled, never a surprise.” This module makes those MEASUREMENTS:

• DramTimings — an LPDDR5X-class timing table (one struct of data, so the memory architect’s corrections drop in as numbers, not code); • schedule / schedule_ordered — the compile-time command scheduler: stream descriptors (the Wave-1 static schedule’s vocabulary) → a fully TIMED command stream with bank-rotated row pipelining and per-bank refresh placed into planned slots; • check_legal — an INDEPENDENT per-command legality checker (tRCD/tRP/tRAS/ tRC/tRRD/tFAW/tCCD, data-bus occupancy, refresh deadlines) — the scheduler is never trusted to grade its own homework; • DeviceModel — a bank-state device that EXECUTES a timed stream and reports every data-beat time: the zero-jitter fact is planned == executed, cycle for cycle; • blacklist remapping — a compile-time row-remap around known-bad rows: the same payload moves, legally, with a measured efficiency delta (yield-by-recompile).

Everything is a pure function of its inputs — deterministic by construction, like the rest of the stack. Wave 3 grows the certified-SAT legality obligation and the in-order executor RTL on top of these exact command streams.

Structs

ComputeDramTiming

The sub-JEDEC violation window that triggers the ComputeDRAM effect, in controller cycles.

DeviceModel

A bank-state DEVICE that executes the plan and reports each data burst’s completion cycle. The zero-jitter fact: these times equal the plan’s own (cas.at + data_cycles) exactly — the device adds nothing and guesses nothing.

DramTimings

LPDDR5X-class timing parameters, in CONTROLLER CLOCK CYCLES, plus geometry. Values are engineering-realistic for an LPDDR5X-6400-class part driven by a controller clock where one RD/WR burst (BL16) occupies data_cycles on the bus — the table is DATA for the memory architect to correct, and every measurement in this module re-derives from it.

Efficiency

The measured outcome of a plan.

Gather

The dynamic tail: explicit addresses (a pointer-chase), one element each.

RowStore

A functional model of DRAM rows — the ComputeDRAM ORACLE the real silicon is measured against. Each row is a bit vector packed into words u64 words.

StreamDesc

A compile-time transfer descriptor — the vocabulary the Wave-1 static schedule hands to the memory edge: count elements of elem_bytes from base, advancing stride_bytes per element (stride == elem ⇒ sequential; stride > row ⇒ row-per- element; the dynamic tail is modeled as an explicit gather list, see Gather).

TimedCmd

A command with its planned issue cycle. The PLAN is the artifact: Wave 3 proves windows of it timing-legal in the certified SAT, and the executor RTL runs it in order with no interpretation.

Enums

ComputeDramOp

A bulk in-DRAM operation over whole rows of one bank. RowCopy is RowClone; And/Or/Maj are the triple-row-activation majority reductions (And/Or assume a preset control row established by a prior RowCopy — wired in the Phase 5 lowering).

DramCmd

One DRAM command.

VisitOrder

How multi-stream access lists are ordered into the plan.

Functions

check_legal

The INDEPENDENT legality checker — a total function over the plan, sharing no code with the scheduler. Returns the first violation as Err(description).

delta_encode

Encode a timed plan as executor words: [delta:24][op:3][bank:5][row:32]. delta = cycles after the PREVIOUS command (first word: cycles after reset). op: 0=ACT 1=RD 2=WR 3=PRE 4=REFpb.

emit_computedram_stream

Emit the raw, deliberately timing-VIOLATING command stream that triggers op on real DRAM: an ACT → PRE → ACT (…) cadence with sub-tRAS/sub-tRP gaps. The stream is NEVER JEDEC-legal (that is the point) — check_legal rejects it by design.

emit_dram_executor_testbench

A self-checking testbench: a ROM of REAL plan words (from delta_encode) drives the executor; the bench asserts every issue arrives IN ORDER with the exact opcode/ bank/row of its word, and prints PASS/FAIL. (Absolute-time equality to the plan is the Rust-side lock; the bench pins order + payload + one-issue-per-word in RTL.)

emit_dram_executor_verilog

The dumb in-order executor: a countdown FSM. It loads the next word, waits exactly delta cycles, strobes the command pins, and acks the word — in arrival order, by construction (there is no other datapath). The rung-3 controller.

map_addr

Address → (bank, row): rows rotate across banks so sequential rows pipeline (bank k streams data while bank k+1 activates). A compile-time-known mapping — the schedule depends on it, and so does the blacklist remap.

measure

planned_beats

Planned data-beat completion times straight from the plan (what the compiler promises); DeviceModel::execute is what the device delivers.

schedule

The compile-time scheduler: bursts grouped into row visits, rows pipelined across banks (ACT ahead under tRRD/tFAW while the data bus streams), refresh co-scheduled per bank into planned slots before every deadline. Returns the timed plan.

schedule_ordered

schedule with an explicit multi-stream visit order (see VisitOrder).

standard_report

The standard measurement scenarios — kernel-shaped traffic classes, each checked legal and measured. Returns a stable JSON document (pure function of the timing table; no clocks, no randomness) — the benchmarks/results/dram_sim.json artifact.

word_majority

Bitwise majority of three words — the sense-amp reduction ComputeDRAM performs per bit.