Module ddr4_jedec 

ddr4_jedec — a DDR4 channel’s timing at its clock, the JESD79-4 command rules a trace is held to, and the in-order controller that turns line streams into commands on it.

Ddr4Grade is a channel as its controller is configured: its geometry (bank groups, banks, rows, columns, bus width), its latencies (CL, CWL, the command-address parity latency), its datasheet minimums in picoseconds or in clocks as the configuration states them, and how many memory clocks one controller clock spans. Ddr4Grade::at clocks it: every picosecond minimum rounds up to whole clocks at the memory clock, tRTP to no fewer than four, tRC is tRAS + tRP where the configuration names none, and tREFI rounds down.

BusChecker replays a command trace against the clocked rules, one command at a time, and stops at the first violation; check_bus runs it over a whole trace. Scheduler is the controller: one column command a line in the order the lines come, each at the earliest clock its rules and the data bus allow; a line’s row opened (and the bank’s other row closed) at the earliest clock its rules allow once the line is within LOOKAHEAD lines of the column commands, so row commands run ahead of the data and hide behind it; one command a clock; an all-bank refresh, after precharging every open bank, as each refresh interval comes due. It releases its commands in clock order once no later decision can come before them, so a stream of any length runs through the checker in bounded memory (measure).

The rules are JESD79-4’s for one rank, a fixed burst of eight, additive latency 0 and a one-clock write preamble (the D5005 controller’s MEM_DDR4_WRITE_PREAMBLE 1), and agree with Ramulator 2’s DDR4 constraint table: read latency CL + PL, write latency CWL + PL; column to column tCCD_L within a bank group and tCCD_S across; WRITE to READ WL + BL/2 + tWTR_L within a bank group and tWTR_S across; READ to WRITE RL + BL/2 − WL + 2; READ to PRECHARGE tRTP; WRITE to PRECHARGE WL + BL/2 + tWR; ACT to column tRCD; ACT to PRECHARGE tRAS; PRECHARGE to ACT or REFRESH tRP; ACT to ACT tRC in one bank, tRRD_L within a bank group, tRRD_S across, and no fifth ACT within tFAW of the fourth before it; REFRESH with every bank precharged, and no command for tRFC after it; no two bursts on the data bus at once. A PRECHARGE to a bank with no open row is legal and changes nothing but its tRP. The refresh account starts at cycle 0 with the device freshly refreshed: each tREFI that passes owes one REFRESH, each REFRESH pays one, at most eight may be owed at any clock and at most eight paid ahead (one past that pays nothing). That bound keeps every row open less than 9 × tREFI, which is tRAS’s maximum, so tRAS’s maximum needs no rule of its own.

Structs

BusChecker

The JESD79-4 rules of one channel, held over a trace one command at a time.

Ddr4Facts

What a legal trace put on the channel: its commands by kind, the bursts that turned the data bus around, the clocks its bursts held the data bus, and the clock after its last data or command.

Ddr4Grade

A DDR4 channel as its controller is configured: geometry, latencies and timing minimums (picoseconds unless named in clocks).

Ddr4Timed

A command and the memory clock it issues on.

Ddr4Timing

A channel clocked: every rule in whole memory clocks.

Location

Where a line lives: bank group, bank within it, row, and the burst’s first column (a multiple of eight).

Scheduler

The controller model: lines in, commands out in clock order.

Enums

Ddr4Cmd

One command on the channel. PreAll precharges every bank; Ref is an all-bank refresh.

Constants

BL

Beats in a burst: the burst length is fixed at eight (MEM_DDR4_BL_ENUM DDR4_BL_BL8).

D5005_EMIF_IP

Where Ddr4Grade::D5005_EMIF is read from.

LOGGED_KINDS

Clocks a command kind is logged as by verilog_model: ACT, READ, WRITE, PRECHARGE, PRECHARGE ALL, REFRESH.

LOOKAHEAD

Lines the controller model holds ahead of its column commands, whose rows it may open early. Modeled: the depth of the hard controller’s command queue is not in its configuration.

REFRESH_POSTPONE_MAX

The REFRESH commands JESD79-4 lets a controller owe, and the most it may pay ahead, in fixed 1x mode.

REFRESH_PULL_IN_MAX

Functions

check_bus

Hold trace to the JESD79-4 rules of t: the first violation, or what the trace put on the channel.

locate

A line (one burst) by the controller’s address order, chip select, row, bank, column, bank group from the most significant end (CTRL_DDR4_ADDR_ORDER_ENUM DDR4_CTRL_ADDR_ORDER_CS_R_B_C_BG): consecutive lines take the bank groups in turn, then the bursts of a row, then the banks, then the rows. Lines past the channel’s last wrap.

measure

The controller’s trace for streams held to the rules as it is issued, never held whole: what it put on the channel, or the first rule it broke.

schedule

The controller’s trace for streams (byte addresses in one channel, line_bytes to a burst) at LOOKAHEAD.

stream_lines

The lines a stream touches, in its order, with its direction: every line any of its elements covers, a line that consecutive elements share once.

verilog_model

A DDR4 channel behind an Avalon-MM slave for simulation, scheduled by this module’s controller model: every line a burst brings is issued as Scheduler::line_at issues it at the memory clock the slave takes it (four to a controller clock), a write’s data is stored as it is taken, and a read’s data, as the memory held it when the read was taken, returns in order PIPE controller clocks after the controller clock its burst leaves the data bus in. With LOG set it writes, to <LOGFILE>_<ID>.log, every line it schedules (L line write arrive column) and every command it places (C clock kind group bank row-or-column, the kind an index of LOGGED_KINDS).