Struct Ddr4Timing 

pub struct Ddr4Timing {

    pub grade: Ddr4Grade,
    pub rl: u64,
    pub wl: u64,
    pub trcd: u64,
    pub trp: u64,
    pub tras: u64,
    pub trc: u64,
    pub trrd_s: u64,
    pub trrd_l: u64,
    pub tfaw: u64,
    pub tccd_s: u64,
    pub tccd_l: u64,
    pub twr: u64,
    pub twtr_s: u64,
    pub twtr_l: u64,
    pub trtp: u64,
    pub trfc: u64,
    pub trefi: u64,
}

A channel clocked: every rule in whole memory clocks.

Fields

grade: Ddr4Grade

rl: u64

wl: u64

trcd: u64

trp: u64

tras: u64

trc: u64

trrd_s: u64

trrd_l: u64

tfaw: u64

tccd_s: u64

tccd_l: u64

twr: u64

twtr_s: u64

twtr_l: u64

trtp: u64

trfc: u64

trefi: u64

Implementations

impl Ddr4Timing

pub fn banks(&self) -> u32

pub fn lines(&self) -> u64

Lines (bursts) the channel addresses: every bank’s rows’ columns in bursts of eight.

pub fn burst_bits(&self) -> u64

Bits a burst moves: eight transfers of the channel’s width.

pub fn burst_ck(&self) -> u64

Clocks a burst holds the data bus.

pub fn write_to_read(&self, same_group: bool) -> u64

WRITE to READ: WL + BL/2 + tWTR_L within a bank group, tWTR_S across.

pub fn read_to_write(&self) -> u64

READ to WRITE, any bank: RL + BL/2 − WL + 2.

pub fn write_to_precharge(&self) -> u64

WRITE to PRECHARGE, one bank: WL + BL/2 + tWR.

pub fn controller_ck(&self, mem_ck: u64) -> u64

Controller clocks mem_ck memory clocks take, rounded up.

pub fn peak_bytes_per_s(&self, line_bytes: u64) -> f64

Bytes per second the data bus carries at full use, line_bytes of every burst being data.

Trait Implementations

impl Clone for Ddr4Timing

fn clone(&self) -> Ddr4Timing

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for Ddr4Timing

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl PartialEq for Ddr4Timing

fn eq(&self, other: &Ddr4Timing) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Serialize for Ddr4Timing

fn serialize<__S>(&self, __serializer: __S) -> Result<__S::Ok, __S::Error>

where __S: Serializer,

Serialize this value into the given Serde serializer.

impl Copy for Ddr4Timing

impl Eq for Ddr4Timing

impl StructuralPartialEq for Ddr4Timing