Module jit 

J1: the straight-line micro-op compiler — bytecode in, native code out.

MicroOp is the JIT’s input IR: the integer subset of the bytecode VM’s register operations. compile_straightline lowers each op to a fixed stencil micro-sequence over the frame/operand-stack machine model and glues the result into one executable chain:

LoadConst{dst,v}  →  const(v); slot_set(dst)
Move{dst,src}     →  slot_get(src); slot_set(dst)
Add{dst,l,r}      →  slot_get(l); slot_get(r); addi; slot_set(dst)
…                    (Sub/Mul/Lt/Eq identical shape)
Gt{dst,l,r}       →  slot_get(r); slot_get(l); lti; slot_set(dst)   (swap)
Return{src}       →  slot_get(src); return

Anything outside this subset is the caller’s tier-up bail (None from the adapter) — the VM keeps running it.

Structs

CompiledChain

A compiled chain plus its side-exit status cell (present only when the program contains checked ops). The deopt stencil stores 1 through the patched cell address; CompiledChain::run_with_frame reads-and-resets it after every run.

Enums

AffOp

The index-arithmetic shape folded into a fused MicroOp::ArrLoadAffine. The computed 1-based index is (frame[a] OP frame[b]).wrapping_add(c) for a two-slot op, or frame[a].wrapping_add(c) for AffOp::None (a single slot plus a constant). The op wraps with the kernel’s exact i64 semantics so the load is bit-identical to the un-fused index arithmetic + ArrLoad.

ChainOutcome

What one chain run produced.

Cmp

Comparison kinds for MicroOp::Branch.

FOp

The float binary operation of a fused MicroOp::ArrLoad2F.

IOp

The integer binary operation of a fused two-buffer MicroOp::ArrLoad2: frame[dst] = a[i-1] <op> b[j-1], the two elements loaded from two (possibly distinct) pinned 8-byte int buffers. Add/Mul commute; Sub does not (it only fuses a[i] - b[j]).

JitCompileError

Compile errors — structural, found before any code is emitted.

MicroOp

The integer straight-line subset the J1 compiler accepts.

RmwOp

The operation of a fused read-modify-write MicroOp::ArrRMW: buf[idx-1] = buf[idx-1] <op> operand. The INT ops (Add/Sub/Mul wrap as the kernel’s i64 arithmetic; And/Or/Xor bitwise) treat the element and operand as raw i64; the FLOAT ops (AddF/SubF/MulF) reinterpret both as f64 (the nbody velocity/position-update idiom). Sub/SubF are the only non-commutative members — the peephole fuses them only when the loaded element is the LEFT operand.

StrSrc

The source operand appended by a MicroOp::StrAppend — the right-hand side of a Set text to text + <s> in a pinned mutable-Text build loop.

Constants

BAKED_CALL_DEPTH

The kernel’s locked maximum LOGOS call depth, BAKED into the precise and self call stencils (their holes are all spoken for, so the limit cannot be a runtime hole). It mirrors logicaffeine_compile::semantics::MAX_CALL_DEPTH and the matching constant in stencils/int_stencils.rs; the callers in the JIT crate pass that same value, asserted here at stencil selection so a drift fails loudly instead of silently capping native recursion at the wrong depth (which would diverge from the kernel’s depth-exceeded error).

Functions

compile_straightline

The returned chain is run with CompiledChain::run_with_frame; the frame’s slots are the program’s registers (inputs pre-loaded by the caller, outputs visible after the run). Programs containing checked ops (Div/Mod) get a status cell and a shared side-exit terminal; their runs can report ChainOutcome::Deopt.

compile_straightline_coded

Like compile_straightline_with, with an optional per-op DEOPT CODE table (parallel to ops). An op whose code is not the plain marker 1 side-exits through its own terminal piece storing that encoded value — the function tier encodes (bytecode_pc << 2) | 3 so the VM can resume precisely. None (and code 1) keep the shared replay terminal.

compile_straightline_pinned

REGISTER-THREADING compilation (EXODIA 3.1): up to four frame slots are PINNED into the threaded registers r0..r3 for the whole chain. Pinned operands ride registers through the generated location-variant stencils; ops outside the variant families (Div, arrays, calls, …) spill the pinned operands they read and reload the pinned slots they write, so every memory-form piece still sees a coherent frame.

compile_straightline_pinned_float

The full register-threading compiler with BOTH integer pins (pins, threaded through the GP registers r0..r3) and FLOAT pins (fpins, threaded through the XMM registers f0..f3). The two budgets are independent — the threaded ABI carries fn(base, sp, r0..r3, f0..f3), so base/sp consume 2 of the 6 GP arg registers (leaving r0..r3) while all four XMM pins sit in the 8 free XMM arg registers and never compete with the integer pins.

compile_straightline_pinned_with

compile_straightline_pinned with a SHARED status cell (the function tier’s deopt/call seam). Integer/bool slots only — no XMM float pins.

compile_straightline_with

compile_straightline with a caller-supplied (per-program) status cell, so every chain of one program — and the call stencils between them — share a single side-exit channel. The cell’s address is what MicroOp::Call::status_addr must carry.

magic_eval

Evaluate the unsigned magic reciprocal for MicroOp::MagicDivU: x / c when mul_back == 0, else x % c (mul_back == c). The dividend is reinterpreted as u64, sound because the op is emitted ONLY for a proven non-negative x (the i64 bit pattern equals the value, and unsigned and signed-truncating //% agree there). The remainder is x - q*c in wrapping i64 (its low 64 bits equal the u64 difference). The more encoding is the logicaffeine_data::LogosDivU64 one: low 6 bits = shift, 0x40 = the 65-bit add-marker path, 0x80 = the pure-shift power-of-two path.

reference_eval

The reference evaluator — the independent model every differential runs against. Deliberately the dumbest possible implementation: a pc loop. fuel bounds the step count (None when caught in a loop that long). A zero divisor also yields None — the reference’s model of the chain’s side exit (differentials feed nonzero divisors when comparing values, and assert Deopt agreement when not).

Type Aliases

Slot

Frame slot index (a VM register number).