Struct SiteSpec 

pub struct SiteSpec {
    pub local_mem_bytes: usize,
    pub local_mem_opt_in_bytes: Option<usize>,
    pub acc_tiles: usize,
    pub fp32_acc_halves_acc_tiles: bool,
    pub movement_engines: u8,
    pub nocs: u8,
    pub credit: Option<CreditLatency>,
    pub local_mem_read_latency: Option<u32>,
    pub mem_banks: usize,
    pub vector_lanes: usize,
    pub int_compute: Option<Precision>,
    pub multiplier: Option<(u32, u32)>,
}

What one site holds.

Fields

local_mem_bytes: usize

Local memory budget for buffers (L1 / shared memory / BRAM), in bytes.

local_mem_opt_in_bytes: Option<usize>

A larger budget available on explicit opt-in (a GPU’s dynamic shared memory), if any.

acc_tiles: usize

Accumulator capacity in native tiles (DST register file / register fragments / systolic columns).

fp32_acc_halves_acc_tiles: bool

Accumulating in fp32 halves the accumulator capacity (Tensix DST).

movement_engines: u8

Independent data-movement engines per site (Tensix: RISCV_0 + RISCV_1).

nocs: u8

Network-on-chip channels a site can drive.

credit: Option<CreditLatency>

Declared credit-loop latencies, when the part’s are known. None means undeclared, NOT zero.

local_mem_read_latency: Option<u32>

Cycles from a read address to its data in the site’s local memory, where the lowering schedules each read itself: Some(0) for a flop array read combinationally, Some(1) for a synchronous SRAM or block RAM. None where the hardware sequences its memory reads and the lowering never sees their timing.

mem_banks: usize

The banks the site’s local memory interleaves its elements over, element e in bank e mod banks: a power of two, the consecutive elements one cycle reads or writes wherever the run starts. 1 where a memory serves an element a cycle, or the hardware sequences its own accesses.

vector_lanes: usize

The lanes of the site’s vector unit: the widest run of consecutive coordinates its Generic unit takes a point, a power of two no wider than the banks, sized to the part as its PE array is — each lane is a copy of every body the unit computes. 1 where the site has no vector unit.

int_compute: Option<Precision>

The one integer width the site’s elementwise datapath computes in, where an integer it stores is the integer it computes and nothing narrower widens on its way in: an RDU’s PCU computes integers in its index datatype (RduChipFacts::index_datatype, INT32). None where a narrower stored integer widens as it is read — a GPU’s registers, the fabric’s sign extension — so a buffer may be stored at any integer the datapath lists.

multiplier: Option<(u32, u32)>

The widest signed product one multiplier slice of the site takes, (wide, narrow) operand bits: a 7-series DSP48E1’s 25 × 18. Synthesis splits a wider product over a cascade of slices. None where the site’s multiplies are no fixed slices — standard cells, a GPU’s units.

Trait Implementations

impl Clone for SiteSpec

fn clone(&self) -> SiteSpec

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for SiteSpec

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl<'de> Deserialize<'de> for SiteSpec

fn deserialize<__D>(__deserializer: __D) -> Result<Self, __D::Error>

where __D: Deserializer<'de>,

Deserialize this value from the given Serde deserializer.

impl PartialEq for SiteSpec

fn eq(&self, other: &SiteSpec) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Serialize for SiteSpec

fn serialize<__S>(&self, __serializer: __S) -> Result<__S::Ok, __S::Error>

where __S: Serializer,

Serialize this value into the given Serde serializer.

impl Copy for SiteSpec

impl Eq for SiteSpec

impl StructuralPartialEq for SiteSpec