Module rdu_chip 

RduChipFacts — ONE source of facts for the SambaNova RDU family, from which BOTH chip descriptors (the spatial mesh SpatialTarget and the scalar-fabric envelope FabricTarget) are derived.

Every number is a Fact with a provenance: Published reads a vendor document named in the chip’s cites; Modeled fills a gap the public record leaves and says what it was inherited from. Nothing here is a measurement of the chip and nothing is a time — the descriptors, the neutral artifact and the fit report all label what they carry, and the locks reflect over the serialized facts so a number without a citation cannot land.

The unit model (RduUnitModel) is what the public record does not say about a PCU, a PMU and the mesh — inherited from the open RDU, Plasticine (Prabhakar et al., ISCA 2017): a six-stage SIMD pipeline of sixteen lanes, a 16-bank × 4096-word scratchpad with a four-stage address datapath, double-buffered as the SN50 public description says. The credit-loop latencies are None — undeclared, NOT zero — until the SDK names them; then RduChipFacts::with_credit drops the number in as data and every derived figure (rdu_ii_report, the descriptors, the envelope) follows without code.

rdu_ii_report is the II view of a placed SpatialProgram on this unit model, built on the same models the Plasticine lane uses — metapipeline for stage II and N-buffer depths, pmu for bank conflicts, and choreography::credit_depth for the bandwidth-delay solve. MODELED: the model’s cycles, never a simulation of the chip.

Structs

Fact

A number with its provenance and its source.

OtherFigure

A figure a source states for a fact other than the one the fact carries: superseded by a later source, or one of two current figures the sources disagree on. Kept beside the facts, so no published figure is lost.

RduChipFacts

The facts of one RDU generation.

RduCreditRow

One IR edge’s credit loop on the unit model.

RduIiReport

The II view of a placed program on one RDU’s unit model — the numbers an RDU engineer asks for first, every one MODELED.

RduIiRow

One compute stage’s timing on the unit model.

RduUnitModel

What the public record does not say about a PCU, a PMU and the mesh — every field modeled and cited, until an SDK number replaces it as Published data.

ScaleUp

How the chips connect beyond the node count: the published rack topology and the scale-up fabric per RDU. Present only where the vendor tabulates the links (the SN50); the SN40L’s per-link fabric is not.

Enums

Provenance

Where a number comes from, strongest first: read from a public source, computed from read numbers, measured by a run, or a model’s. The order is the trust order, so a figure computed from several facts is as strong as the weakest of them: their max.

RduChip

The RDU generations the facts describe.

Constants

BINARY

How every capacity is read: as the vendor counts it, in powers of two. SambaNova states 1040 PMUs of 512 KB and 520 MB of SRAM [DIAYN26], which agree only when a MB is 1024 KB; the SN40L paper writes the same figures as MiB, GiB and TiB in its prose and as MB, GB and TB in its table [SN40L24]; an HBM2E stack holds 16 GiB.

HBM_STACKS

The HBM stacks an RDU’s 64 GiB is laid out as for a model that counts channels: four 16 GiB HBM2E stacks.

Functions

rdu_ii_report

The II view of p on facts’ unit model. One row per compute-role stage: latency = the PCU pipeline depth (+ the reduction tree, ⌈log₂ lanes⌉, when the stage folds an axis); resource II from the unit model’s occupancies; recurrence II = pipeline depth + register turnaround when the stage reads a buffer it also writes (a spilled partial, an in-place update); memory II from the stage’s vector accesses under the PMU’s strided banking. Then the pipeline’s II, Spatial’s N-buffer depths over compute→compute edges, and the credit-loop depth of every IR edge.

witnessed_precisions

The precisions the descriptors advertise, as a set.