Module metapipeline 

The metapipeline initiation-interval (II) model — P1 of the Plasticine lane, and the question an RDU engineer asks first: how often can a pipelined stage accept a new iteration, and how deep must the buffers between stages be?

Definitions follow Spatial (Koeplinger et al., PLDI 2018, §4): each primitive has a resource II (1 for a fully pipelined unit, its occupancy for a sequential one); a loop-carried dependency has a recurrence II equal to the path length from the read of a carried value to its write; a controller’s II is the maximum of all resource IIs and all recurrence IIs; an outer (metapipelined) controller’s throughput is set by its slowest stage; and a memory written in stage i and read in stage j needs j - i + 1 buffers (N-buffering — adjacent stages double-buffer).

The model is built FROM the certified fabric IR (LoopFabric): the body is the stage’s datapath, the carried state registers are the recurrences, and UnitModel supplies per-cell latency / occupancy. eval_loop_fabric_at_ii is the executable meaning of the number: a cycle-timed pipelined execution that issues one iteration every ii cycles and reads whatever a carried register holds at issue time — at the modeled II it reproduces the sequential oracle exactly, one cycle faster it reads stale state (a hazard), so metapipeline_lock proves the II is neither optimistic nor vacuous. MODELED: cycle counts here are the model’s, never a Plasticine simulation.

Structs

Metapipeline

A metapipeline: stages in issue order, with the producer→consumer buffer edges between them.

PipelinedRun

The result of a cycle-timed pipelined run of a counted loop.

Stage

One metapipeline stage’s timing.

UnitModel

Per-cell timing: how many cycles a cell’s result takes (latency) and how many cycles the cell’s unit is busy per iteration (occupancy, the resource II). A fully pipelined unit has occupancy 1 whatever its latency; a sequential unit (an iterative divider) has occupancy == latency.

Functions

eval_loop_fabric_at_ii

Execute a counted loop as a pipeline issuing one iteration every ii cycles. Iteration t issues at cycle t*ii, reads each carried register’s value as of that cycle (the latest write whose completion cycle <= the issue cycle), and completes register k’s write at t*ii + depth_k. With ii >= the recurrence II every read sees the previous iteration’s write and the result equals eval_loop_fabric; below it, reads are stale (hazards).

loop_stage

Model one counted loop as ONE metapipeline stage.