pub fn image_digest(files: &[(String, String)]) -> StringExpand description
The identity of a board build: the sha256, in hex, of every file synthesis reads — in name order, each its name, a
zero byte, its text and a zero byte — with every Verilog file’s simulation-only regions (synthesis translate_off
through synthesis translate_on) taken out, so a check only a simulation runs moves no bitstream’s identity.