Function chip_board_verilog 

pub fn chip_board_verilog(lat: u64) -> String

chip_board: one chip’s program of a program split over chips (compile_program_to_chips), its host port and its halts driven over the serial pair. Beside I, W and R as decode_board serves them:

Command	Arguments	Reply
X run	—	x, the link it halted at (2), or 0xFFFF at its end, then the cycles it has run (4)

X starts a step — a reset and a start — when none is running, and otherwise continues the halted fabric past its halt; either way it replies once the fabric halts again or finishes. The cycles pause while the fabric is halted, so each reply counts the cycles the program has run (fabric_cycle_segments). A halted fabric’s memories are still, so the host reads what the chip sends and writes what it receives with R and W between runs.