Function floor_divider_verilog 

pub fn floor_divider_verilog(name: &str, wa: u32, wb: u32, wq: u32) -> String

A pipelined signed floor divider q = ⌊a / b⌋ — a of wa bits, b of wb, q of wq — taking a pair a cycle and returning each quotient floor_divider_latency cycles after its operands.

It divides the magnitudes by restoring division, a quotient bit a stage, then floors: where the signs differ the quotient is negated, and one less again where a remainder is left. A quotient proven to fit wq bits has no bit above them, so the dividend’s bits above them start the remainder and the stages walk only the wq below. A divisor of zero is the evaluator’s error; its quotient is whatever the stages make of it.