Module fabric 

Our fabric: the spatial IR as synthesizable Verilog.

Every IR object is one RTL object, and every choreography op is a step of the engine that owns it: a site is a module holding its tensor memories, its page FIFOs, its semaphores and its engines; an engine is a module printed once per engine-program class and instantiated per site with the site’s work as parameters; a multicast group is one bus at the top; a tile matmul is the proven loadable weight-stationary PE array shaped to the block, and a matmul of one row — a matrix-vector product — multiplies each operand element as it lands instead (Ctx::matvec). The discrete-event twin (fabric_cycle_model) walks the same micro-programs with the same durations and stall rules, so its count IS the RTL’s count.

A FIFO is its control — counts, reservations, the slot it reads — and its pages live in one of its site’s pools: the buffers of one phase take pools 0, 1, 2, …, so a site has as many page memories as its busiest phase has buffers (site_pools).

A site’s memories interleave their elements over SpatialProgram::mem_banks banks, and a page starts on a word. A run of w elements from a multiple of w — a tile row, a page’s span, an accumulator row’s columns — moves in one cycle, each bank at the one row every bank of the port shares. A walk moves the widest run every row it starts is aligned to in each memory it touches (Ctx::run), and each port carries only the run widths its ops move (port_widths), so no port rotates a lane past its own word.

The Generic unit is a vector unit as wide as those runs: an op takes a run of one axis’s coordinates a point, a lane a coordinate, where its slots read that axis as runs or as one element, and a slot that gathers reads, in each lane, the element its own index names through a read port of its own (lanes_of, gather_lanes). A reduced lane axis folds its lanes through a tree into the op’s own fold; a parallel one keeps a fold per lane and writes a run of columns. A site of one bank prints the scalar unit, byte for byte.

An op that carries data takes states of its own; an effect that only signals it — a push, a pop, a semaphore’s increment — commits in that op’s last cycle, and the op’s last cycle also takes the loop bound after it and checks the guards it reaches, so the sequencer spends a cycle only on work or on a wait that is real. That last cycle is a register the op’s duration counts down to, so nothing decodes the state in front of the units it resets.

Modules

budget

The programmable-part resources a fabric program spends, counted from exactly what the printer declares, so a program too big for its part is refused before a line of RTL is printed.

Structs

CycleBreakdown

Where a run’s cycles go: its total, the twin’s, and each engine’s cycles by activity — every engine accounting for every cycle of the run.

EngineCycles

One engine’s cycles of a run, by what it did in each.

FabricBackend

VerilogArtifact

Enums

Activity

What one engine did in one cycle of the twin.

Functions

fabric_cycle_breakdown

fabric_cycle_model with each engine’s cycles attributed: what it ran, what held it, when it was done. None where the fabric does not lower p.

fabric_cycle_model

Predicted RTL cycles of p: every engine walks its micro-program in lock-step cycles against registered buffer and semaphore state (an effect lands the cycle after it is issued), exactly as the FSMs do.

fabric_cycle_segments

The fabric’s cycle counter at each halt of p’s program (LinkPoint), in order, then at its end: what its board replies to each X. The counter pauses while the fabric is halted, so each count is the cycles the program has run. One count — fabric_cycle_model’s — for a program that halts nowhere; None where the fabric does not lower p.

fabric_cycles_within

The twin’s cycles for p where it finishes within limit cycles; None where it does not, or where the fabric cannot lower it. The twin stops at the limit, so asking costs at most limit cycles of simulation.

fabric_micro_listing

Each engine’s micro-program as the twin and the printer walk it: one line per state — the op, and a fixed op’s cycles; a tile walk’s run, and an accumulator walk’s region columns and run. None where the fabric does not lower p.

fifo_control_verilog

A page FIFO’s control, module name: depth pages, and the reservations, pushes, waits and pops that are the IR’s ops — free, count, the slot the next fill takes and the slot the next read takes. Its pages live in the pool memory its phase colors it into (site_pools).

floor_divider_latency

Cycles from a pipelined floor divider’s operands to its quotient: a stage for the magnitudes and the quotient’s sign, a stage per quotient bit — the wq bits the proof bounds the quotient to, never more than the dividend’s wa — and a stage for the floor.

floor_divider_verilog

A pipelined signed floor divider q = ⌊a / b⌋ — a of wa bits, b of wb, q of wq — taking a pair a cycle and returning each quotient floor_divider_latency cycles after its operands.

host_word

The word of a site’s image of t that holds element (i, j) — tiles in row-major order, a row of tiles at the tensor’s pitch (tensor_pitch), each tile’s elements row-major within it — and so the address a host writes or reads that element at.

input_hex_files

$readmemh files for the program’s input tensors, in the sites’ tile-major element order.