Module vector_side 

A hybrid engine’s vector jobs in the user clock (super::engine::Streaming::vectors): logos_vector_side runs a crate::spatial::decode_engine::machine::Job::Vector job as the core’s vector-job states do — the job’s descriptors from the job words, then each pass of a row and a head: the loads into the vector unit’s registers, the micro-program on the user clock’s vector unit (logos_simd_p, super::simd::simd_p_verilog), the stores — on its own copies of the core’s tables, written as the core’s are, the token-row store’s user-clock port and the fast port onto the channels (super::super::physical::fast_port_verilog).

A load or a store into the token-row store streams a beat a clock. A load from the memory asks for a line whenever the port takes one and writes each line into its register as it comes back, in order; a ring row stored in binary16 is widened half a line a beat. A store into the memory reads a beat a clock while the queue its beats wait in has room for every beat on its way, each beat’s binary16 halves and int8 codes out of pipelined units; it gathers its beats in one line until a beat leaves the line or the pass ends, taking a beat a clock: a whole line goes to the write queue the clock the queue is free, a part of one is read once every write before it is on the card, merged and written. A ring load whose row’s sequence stored a ring row earlier in the job waits until every write before it is on the card, so a sequence’s next row reads the ring row its last row wrote; no other load reads what a vector job writes (another sequence’s rows touch other rings, tensors and rotary tables are never written), so none waits. A kept load (crate::spatial::decode_engine::machine::VectorJob::kept: a tensor’s span at stride 0 into a register nothing else writes) is read on the job’s first pass alone. A job whose rows cross nowhere (crate::spatial::decode_engine::machine::VectorJob::chunked) and is deeper than the unit runs its passes once for each chunk of VROWS beats of its vectors, every load and store that chunk’s beats, its kept loads read on each chunk’s first pass; so the unit is as deep as the deepest job that reduces, rotates or turns, not the deepest elementwise one. The products of an element’s place are split into sixteen-bit halves, each sum truncated to the width the core’s expression has, so every place is the core’s.

A side of PASSES above one (super::engine::Streaming::vector_passes) runs a job whose passes stand alone (crate::spatial::decode_engine::machine::VectorJob::grouped, its header’s bit 54) in groups: as many passes as the unit holds rows for, up to PASSES, loaded one after another, each into rows of its own; the micro-program issued once over the group, each instruction taking the group’s passes side by side (logos_simd_p‘s group), each pass’s operations in their own order; then each pass’s stores from its rows and scalars, the line they gather in flushed after each pass as between passes. A pass’s values are the ones it computes alone. The unit holds DEPTH times VROWS rows a register (super::engine::Streaming::vector_depth), so a job whose vectors are VROWS beats deep runs DEPTH passes a group; its chunks and its float matrices’ held inputs stay VROWS beats a vector.

A float matrix’s job (a tensor’s row a head dotted with each row’s input, one scalar a pass) runs on a path of its own: every row’s input held, FM_ROWS rows to a group of 16·FM_ROWS lanes and the rows past them in further groups the same lanes take in turn; eight heads’ weight rows streamed a line of each in turn, each line given to the lanes once for each group, every row’s products added in numerics::fdot’s order, every row’s head through the tree into its element. The lines come back into a queue and leave it for the lanes once their head’s last sum of the group has left the add, so a group of fewer heads than the add is deep, or lines bunched by the port, still add each head’s terms one after another. The weights stream once for every row the side holds.

Constants

CONV_LATENCY

Cycles from a conv lane’s operands to its value (logos_conv_lane_p): the products, the four adds one after another, the SiLU.

FM_ROWS

The rows of a float matrix’s job a clock of its lanes takes: its lanes 16·FM_ROWS.

Functions

conv_path_verilog

logos_conv_lane_p and logos_conv_path, a convolution job’s rows through the vector side (super::engine::Streaming::with_conv_path).

vector_side_verilog

The vector side with the vector unit, the block RAM and the functions it is built from.