Module vector 

The vector units’ functions as Verilog, each the same f32 operations in the same order as its numerics function (crate::spatial::decode_engine::numerics): exp, recip, rsqrt, ln, ln1p, softplus, sigmoid and silu, over the engine’s f32 multiply and add, with the integer steps the functions take between them — the nearest integer of an f32, an integer as an f32, a power-of-two scaling — and their tables as ROMs.

The modules are combinational: one function of its operand, so a lock holds each to its numerics function over every class of operand. logos_exp_p, logos_recip_p, logos_rsqrt_p and logos_ln_p are exp, recip, rsqrt and ln for the user clock, an operand a clock on the pipelined units, the same operations in the same order with their integer steps and tables registered between them (EXP_LATENCY, RECIP_LATENCY, RSQRT_LATENCY, LN_LATENCY).

Constants

EXP_LATENCY

Clocks from an operand entering logos_exp_p to its exponential leaving: the range reduction’s multiply, the nearest integer (RNE_P_LATENCY), its f32 (I2F_LATENCY), the two reducing multiplies and subtractions, the polynomial’s three multiply-adds, the table’s multiply and the result registered.

I2F_LATENCY

Clocks from an integer entering logos_i2f_p to its f32 leaving: its magnitude and leading one registered, then the shift and the f32.

LN_LATENCY

Clocks from an operand entering logos_ln_p to its logarithm leaving: the table index registered, the centre’s numerator and the exponent as f32s (I2F_LATENCY), the table’s entries, the centre and the exponent registered, the polynomial’s four multiplies and four subtractions in turn, the three sums with the table’s logarithm and the exponent’s, the result registered.

RECIP_LATENCY

Clocks from an operand entering logos_recip_p to its reciprocal leaving: the seed registered with the operand, the two Newton steps’ multiply, subtraction and multiply each, the result registered.

RNE_P_LATENCY

Clocks from an f32 entering logos_rne_p to its nearest integer leaving: the shifted magnitude and its round bit registered, then the add and the sign.

RSQRT_LATENCY

Clocks from an operand entering logos_rsqrt_p to its reciprocal square root leaving: the seed registered with the operand, the two Newton steps’ four multiplies and subtraction each, the result registered.

Functions

vector_verilog

Every vector-unit module, with the f32 multiply and add they are built from.