Function store_verilog 

pub fn store_verilog() -> String

logos_store_w512 #(D, A): the token-row store’s bank as bram_re_verilog’s logos_bram_re_w512 holds it — its read taken on the edges re is high on and held between them, a write under a byte mask — its word out STORE_READ_LATENCY clocks after its address instead of one. Its words are layers of 512, each a block RAM of its own read every clock (logos_bram_w512_part), so the block takes its read register whole and reads the word before a write of its address in the same clock, as its port does; a layer read under the read enable would hand the block the address register instead and need pass-through logic in the fabric for its read-during-write. Every port is taken into registers a clock before the layers see it, each layer’s write enable decoded there, the read’s address and the write’s row, data and mask copied near the layers they reach (maxfan). Each layer’s word is zero unless the read was of it, and the words are gathered by an OR, STORE_GROUP layers at a time into registers, then across the groups into the word read, which alone is held between the clocks re is high on (the read enable carried beside the read). A write lands a clock after it is asked, as a read does, so each read sees the writes it would if neither waited: a reader that takes its word STORE_READ_LATENCY clocks after its address reads what it read a clock after its address from the bank of one.