Function ram_ce_verilog 

pub fn ram_ce_verilog(widths: &[usize]) -> String

logos_ram_w<W> for an engine whose registers step on the rising edges ce is high on: the read registered on the edges cr is high on, the word held between them, the write on the edges ce is high on. With ce high the user clock’s cycle that ends with an engine step and cr high the cycle after the engine cycle’s middle, a read sees the memory as the step before left it, at an address the registers that step set, as the falling-edge read does.