Function delay_verilog 

pub fn delay_verilog() -> &'static str

logos_delay #(W, D), a word of W bits delayed D clocks (the word itself at depth 0). One or two clocks are a chain of registers. From DELAY_RING_LEAST clocks on the words go round a ring, a memory of the next power of two of D words written a word a clock and read D - 1 words behind the write into its port’s register, the chain’s D·W flip-flops left as the ring’s write address: logos_delay_mlab in MLABs to MLAB_WORDS words whatever its width, and beyond that logos_delay_m20k in M20K blocks from DELAY_M20K_LEAST bits wide and logos_delay_mlab below.