Expand description
The attention unit’s vector path as Verilog: one query head over its sequence’s cached rows, exactly as
crate::spatial::decode_engine::numerics::attend_vector computes it.
Three passes over the positions. The keys stream in, HD/16 beats of sixteen elements a position: each beat’s
products with the head’s queries accumulate in sixteen lanes (element i in lane i mod 16), the lanes fold by the
pairwise tree, the dot times the scale is the position’s score, kept, and the scores’ maximum is taken as the
softmax takes it (a NaN never larger, a largest zero +0). Then each exp(s − max) is kept and summed in sixteen
lanes by position, the sum folded by the tree and its reciprocal taken. Then the values stream in, VD/16 beats a
position: each position’s probability e·(1/Σ) times its row adds into lane position mod 16 of every element,
and the lanes fold by the tree into the head’s output, sixteen elements a beat.
Functions§
- attend_
int8_ p_ verilog logos_attend_int8_p,ATTEND_INT8_VERILOG’s unit for the user clock, with the units it is built from.- attend_
side_ verilog logos_attend_side, a token-row’s attention for a hybrid engine’s fast side (super::engine::Streaming::attention), with the user clock’s unit and quantizer it drives.- attend_
verilog - The unit’s two paths, with the f32 units, the functions, the lane’s one rounding and the block RAM they are built from.